VLSI layouts of complete graphs and star graphs

Abstract

In this paper, we present efficient layouts for complete graphs and star graphs. We show that an N-node complete graph can be optimally laid out using LN2/4] tracks for a colinear layout, and can be laid out in N4/16 + o(N4) area for a 2D layout. We also show that an N-node star graph can be laid out in N2/16 + o(N2) area, which is smaller than any possible layout of a similar-size hypercube. This solves an open question posed by Akers and Krishnamurthy in 1986. Both the layouts of complete graphs and star graphs are optimal within a factor 1 + o(l). 0

Increasing the connectivity of the star graphs

“…One concern about star graphs was their relatively complicated topological characteristics, which led to concerns about an efficient layout for star graphs. References [25,28] studied this problem. In particular, [28] solved an open problem posed by [1] by showing that a star graph can be laid out in an area smaller than any possible layout of a similar-size n-cube.…”

“…References [25,28] studied this problem. In particular, [28] solved an open problem posed by [1] by showing that a star graph can be laid out in an area smaller than any possible layout of a similar-size n-cube. Since the star graphs have order n!, for a particular network application using the star-graph topology, one may face the choice of either too few or too many available vertices.…”

Efficient VLSI layouts of hypercubic networks

“…The inter-cluster links between top-level clusters can be laid out in N 2 =16 + oN 2 area using the layout of an Mnode complete graph [25,27] with multiple edges. When one of the conditions holds, the area for all nuclei does not affect the leading constant of the layout area and the required area is dominated by the top-level inter-cluster links.…”

Two models of two-dimensional bandwidth problems

“…It should be emphasized that the bandwidth embedding here is related to the VLSI layout, but to say rigorously, they are not the same thing. In fact, the edge routings in VLSI layout are not allowed to overlap from each other (with congestion 1) and people are mainly interested in some other objectives (such as layout area, expansion ratio) [1,10,12]. However, in the bandwidth problem mentioned above, we need not consider the edge routings and only the distances are taken into account.…”