VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images

Garimella, Adithya; Satyanarayana, M.; Kumar, Raushan; Murugesh, P.S.; Niranjan, U. C.

doi:10.1109/icvd.2003.1183151

Cited by 34 publications

(8 citation statements)

References 5 publications

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“…Each one of them has relative merits and demerits. Garimella et al [6] implemented a fragile invisible watermarking algorithm based on spatial domain approach using standard ASIC design flow with 0.13 m CMOS technology, and has a die size of 3453 × 3453 2, consumes 37.6 W power. Later on Kougianos et al [7] made a survey on necessity and different goals of hardware realization of digital watermarking.…”

Section: Related Workmentioning

confidence: 99%

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Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

Ghosh

Das

et al. 2014

2014 International Conference on Information Technology

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The additional operation of retrieval of the cover image at the decoder is necessary for lossless watermarking system. Taking into account this major issue, efficient implementation of reversible image watermarking needs to be addressed. This can be solved using hardware implementation. This paper focus on the digital design with pipelined architecture of reversible watermarking algorithm based on Difference Expansion(DE) which is linear and whose running time is O(n). There are three different digital architectures proposed in this paper namely dataflow architecture, optimized dataflow architecture using pipelining and the modified architecture using pipelining. All the three design is implemented on Xilinx based FPGA. To the best of our knowledge this is the first digital design and pipelined architecture proposed in the literature for reversible watermarking using difference expansion.

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Section: Related Workmentioning

confidence: 99%

“…Now is obtained from using (7) in T11. This is then 1-bit left shifted and subtracted from to get (6).After recovering the embedded bit,it is used to recover the original pixels and using (8) and (9) respectively.…”

Section: Fig1(dataflow Architecture Of Embedder)mentioning

confidence: 99%

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

Ghosh

Das

et al. 2014

2014 International Conference on Information Technology

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“…In the given literature, a number of hardware designs for conventional watermarking algorithms have been reported. The Very Large Scale Integration (VLSI) architecture for a conventional watermarking algorithm in the spatial domain proposed by Gerimella et al [10] might be considered as a noteworthy early work. Later, Mohanty et al [11] proposed a watermarking hardware architecture that can insert two visible watermarks into digital images using a spatial domain watermarking technique.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of Digital Images Watermarking System Based on Discrete Haar Wavelet Transform

Hajjaji

Gafsi

Abdelali

et al. 2019

Security and Communication Networks

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In this paper we propose a novel and efficient hardware implementation of an image watermarking system based on the Haar Discrete Wavelet Transform (DWT). DWT is used in image watermarking to hide secret pieces of information into a digital content with a good robustness. The main advantage of Haar DWT is the frequencies separation into four subbands (LL, LH, HL, and HH) which can be treated independently. This permits ensuring a better compromise between robustness and visibility factors. A Field Programmable Gate Array (FPGA) that is based on a very large scale integration architecture of the watermarking algorithm is developed to accelerate media authentication. A hardware cosimulation strategy using the Matlab-Xilinx system generator (XSG) was applied to prove the validity of the suggested implementation. The hardware cosimulation results show the effectiveness of the developed architecture in terms of visibility and robustness against several attacks. The proposed hardware system presents also a high performance in terms of the operating speed.

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“…Tasi and Lu [27] have proposed a DCT domain invisible watermarking chip with TSMC 0.35 µm technology and has a die size of 3.064 × 3.064mm 2 [28]. Garimella et al [29] have proposed a VLSI architecture for invisible fragile watermarking in the spatial domain. The application specific integrated circuit (ASIC) is implemented using 0.13µm technology.…”

Section: Review Of Related Work and Limitationsmentioning

confidence: 99%

Dual purpose FWT domain spread spectrum image watermarking in real time

Maity

Kundu

Maity³

2009

Computers & Electrical Engineering

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Spread spectrum (SS) watermarking for multimedia signal becomes appealing due to its high robustness attribute and is used widely for various applications. Some of these applications essentially demand development of low cost algorithms so that they can be used for real time services such as broadcast monitoring, security in communication etc. In recent time one popular non-conventional application of digital watermarking becomes promising that assesses blindly the QoS (quality of services) of the multimedia services which is expected to be offered by the future generation mobile radio network. Majority of the existing SS watermarking schemes suffer from high computation cost and complexity leading to the difficulty for realtime implementation and limits their usage for the above mentioned applications. This paper proposes Fast Walsh Transform (FWT) based SS image watermarking scheme that serves the dual purposes of authentication in data transmission as well as QoS assessment for digital media through dynamic estimation of the wireless channel condition. Fast Walsh transform offers low computation cost for implementation, smaller change in image (multimedia signal) information due to data embedding and ease of hardware realization. VLSI implementation using Field Programmable Gate Array (FPGA) has been developed to make it suitable for real time implementation.

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VLSI implementation of online digital watermarking technique with difference encoding for 8-bit gray scale images

Cited by 34 publications

References 5 publications

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA

FPGA Implementation of Digital Images Watermarking System Based on Discrete Haar Wavelet Transform

Dual purpose FWT domain spread spectrum image watermarking in real time

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