VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG

Subramanian, P.; Reddy, A Sagar Chaitanya

doi:10.1109/icosp.2010.5657181

Cited by 7 publications

(7 citation statements)

References 7 publications

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“…The proposed design is also smaller and faster than a pure shift-add architecture. In Tables 10 and 11, we show the results of the comparison between the proposed design and other proposed designs, such as the designs from references [6], [7], [8] and [9]. The results show that our design can reach all three design objectives (small area, multiplierless, and low complexity).…”

Section: Benchmarksmentioning

confidence: 81%

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A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

et al. 2012

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Abstract. In the literature, several approaches of designing a DCT/IDCT-based image compression system have been proposed. In this paper, we present a new RTL design approach with as main focus developing a DCT/IDCT-based image compression architecture using a self-created algorithm. This algorithm can efficiently minimize the amount of shifter-adders to substitute multipliers. We call this new algorithm the multiplication from Common Binary Expression (mCBE) Algorithm. Besides this algorithm, we propose alternative quantization numbers, which can be implemented simply as shifters in digital hardware. Mostly, these numbers can retain a good compressed-image quality compared to JPEG recommendations. These ideas lead to our design being small in circuit area, multiplierless, and low in complexity. The proposed 8-point 1D-DCT design has only six stages, while the 8-point 1D-IDCT design has only seven stages (one stage being defined as equal to the delay of one shifter or 2-input adder). By using the pipelining method, we can achieve a high-speed architecture with latency as a trade-off consideration. The design has been synthesized and can reach a speed of up to 1.41ns critical path delay (709.22MHz).

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Section: Benchmarksmentioning

confidence: 81%

“…Byoung-Il Kim, et al [6] have proposed a low-power multiplierless DCT for image/video coders. Subramanian, et al [7] have proposed a VLSI implementation of a fully pipelined multiplierless 2D-DCT/IDCT architecture for JPEGs.…”

Section: Introductionmentioning

confidence: 99%

A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

et al. 2012

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“…By neglecting the scaling factor 112, the I-D 8-point DCT in (2) can beDivided into even and odd parts: [8].For getting all 8 outputs 64 multipliers are used. In decomposed DCT architecture by adding one pre processing unit we have to reduce the multipliers usage by 50 % ( only 32 multipliers used).…”

Section: +-Ieeementioning

confidence: 99%

“…From the equations (3) and (4), it can be stated that the DCT operation involves multiplication of various cosine coefficients with a fixed input sequence. Hence sub structure sharing technique is used to reduce the number of operators [8]. The cosine basis is quantized to 8-bits for energy efficiency.…”

Section: Dct Coefficientsmentioning

confidence: 99%

CORDIC based high speed DCT algorithm

Esakkirajan¹,

Annadurai²

2014

2014 International Conference on Communication and Signal Processing

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CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used in Digital Signal Processing applications. In this paper, we extend the methodology for designing a low-power area-efficient DCT for image compression using only shift registers, and adders! sub tractors and special interconnections. Through hardware synthesis we proved that shift and add based DCT computation is efficient one over conventional multiplier based approach and finally accuracy was measured by comparing PSNR value of reconstructed image with original image using MATLAB.

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“…Another widely used architecture focuses on approximate reconstruction of DCT coefficients through fixed-point representation. Subramanian et al [26] proposed a 2D 8×8 DCT/IDCT VLSI full-pipeline less multiplication architecture, running at a frequency of 166 MHz with a latency of 65 clock cycles. Xing et al [27] combined three approximation methods into a multiplier-less DCT architecture for wireless capsule endoscopy applications.…”

Section: Introductionmentioning

confidence: 99%

Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture

Zhou

Zhang

2022

IEEE Access

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This paper proposes an effective hardware accelerator for 2D 8×8 discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT) using an improved Loeffler architecture. The accelerator optimizes the data stream of the Loeffler 8-point 1D DCT/IDCT according to the characteristics of image and video processing. An 8-stage pipeline structure greatly improves the processing speed by reasonably dividing the number of clock cycles and simplifying the arithmetic operations in each cycle. The multiplication-free approximation of the DCT coefficients is implemented through adders and shifters, combined with both fixed-point and canonic signed digit (CSD) coding. In particular, the proposed fast parallel transposed matrix architecture achieves the function of row-column coefficient conversion with lower circuit complexity. The FPGA implementation of the proposed architecture uses a Virtex-7 XC7VX330T device, running at 288 MHz with a throughput of 558 M Pixel/sec, and a Full HD real-time frame rate of up to 269 fps. Only 33 cycles are required to complete the 8×8 blocks of 2D DCT/IDCT, which can be used as a high-performance hardware accelerator for image and video compression encoding.

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VLSI Implementation of fully pipelined multiplierless 2D DCT/IDCT architecture for JPEG

Cited by 7 publications

References 7 publications

A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

CORDIC based high speed DCT algorithm

Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture

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