A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

Putra, Rachmad Vidya Wicaksana; Mareta, Rella; Anbarsanti, Nurfitri; Adiono, Trio

doi:10.5614/itbj.ict.2012.6.2.3

Cited by 4 publications

(3 citation statements)

References 6 publications

(5 reference statements)

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“…Bit-level optimization is suitable in VLSI, as was found in past researches (e.g. [22]- [24]). As a practical example, Figures 4 and 5 show that the computational state begins at current state P = "000".…”

Section: Viterbi Decodermentioning

confidence: 87%

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Putra

Adiono

2016

J. ICT Res. Appl.

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Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and lowcomplexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

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Section: Viterbi Decodermentioning

confidence: 87%

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Putra

Adiono

2016

J. ICT Res. Appl.

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“…36. IDCT coefficient values are calculated based on multiplication from the common binary expression (mCBE) algorithm 40 in the watermark preprocess unit. The mCBE algorithm leads to a reduction in the area, number of multiplier used and complexity.…”

Section: Fpga Implementation Of the Rvwesmentioning

confidence: 99%

“…To reduce the image size, high frequency components are eliminated without affecting image quality (IQ); DCT compressions are used. Multiplication decompression using the mCBE algorithm architecture design has been clearly explained, 40 and is used to get 2D-IDCT coefficient in the preprocessor module and the embedded process module.…”

Section: D-idct Implementationmentioning

confidence: 99%

Architecture Design and Field Programmable Gate Array Implementation of Removable Visible Image Watermarking for Digital Camera Images Using a Private Key

Merlin¹,

Rajamani²,

Jayanthi³

2014

jist

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A visible watermark conveys ownership information, used to identify the originator of an image. The watermark image is preprocessed and visibly embedded with an original image, before posting on the web for free observation and download. Based on the request of the buyer, the watermark can be removed to restore the unmarked image. A user-key-dependent frequency domain removable visible watermark embedding system (RVWES) is proposed. The user key structure decides both the embedded subset of the watermark and the host information adopted for adaptive embedding. With the correct user key, watermark removal can be carried out for information detection, and the high quality unmarked image can be restored. The proposed approach is mainly designed for the watermarking of digital camera images of various sizes. Pipeline and parallelism mechanisms are used to improve the throughput in the RVWES. The hardware implementation algorithm is tested in a Xilinx Virtex V XC5VlX330 technology based field programmable gate array, with which the throughput achieved is 4.3 Gbit/s with a total area utilization of 17448 BELs. To improve the robustness, a chaotic map is used to shuffle the watermark. The experimental results show that the watermarked image quality is good. Furthermore, the proposed approach is able to resist against a variety of general image processing attacks.

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A configurable and low complexity hard-decision viterbi decoder in VLSI architecture

Putra

Adiono

2014

2014 2nd International Conference on Information and Communication Technology (ICoICT)

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A New RTL Design Approach for a DCT/IDCT-Based Image Compression Architecture using the mCBE Algorithm

Cited by 4 publications

References 6 publications

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

Architecture Design and Field Programmable Gate Array Implementation of Removable Visible Image Watermarking for Digital Camera Images Using a Private Key

A configurable and low complexity hard-decision viterbi decoder in VLSI architecture

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