VLSI implementation of a 16*16 discrete cosine transform

Sun, Ming–Ting; Chen, T.-C.; Gottlieb, A.M.

doi:10.1109/31.92893

Cited by 180 publications

(18 citation statements)

References 8 publications

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“…The inner product expression reformulated with the adder-based DA algorithm is (4) where is the word length of and denotes the -th bit of . Without loss of generality, this equation is expressed in an unsigned fraction form.…”

Section: B Da Formulationmentioning

confidence: 99%

A simple processor core design for DCT/IDCT

Chang

Kung

Jen

2000

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete cosine transform/indiscrete cosine transform (DCT/IDCT) operations in H.263 and digital camera. This design combines the techniques of fast direct two-dimensional DCT algorithm, the bit-level adder-based distributed arithmetic, and common subexpression sharing to reduce the hardware cost and enhance the computing speed. The resulting architecture is very simple and regular such that it can be easily scaled for higher throughput rate requirements. The DCT design has been implemented by 0.6 m SPDM CMOS technology and only costs 1493 gate count, or 0.78 mm 2 . The proposed design can meet real-time DCT/IDCT requirements of H.263 codec system for QCIF image frame size at 10 frames/s with 4:2:0 color format. Moreover, the proposed design still possesses additional computing power for other operations when operating at 33 Mhz.Index Terms-DCT/IDCT, H.263, processor.

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Section: B Da Formulationmentioning

confidence: 99%

A simple processor core design for DCT/IDCT

Chang

Kung

Jen

2000

IEEE Trans. Circuits Syst. Video Technol.

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“…From the simulation results due to Sun et. a1 [5], the word length of the ROM must be at least 9 bits to ensure that the SNR is greater than 40dB. To reduce the error due to recursive computations, we increase the word length of the ROM to 12 bits.…”

Section: Chip Realization and Simulationsmentioning

confidence: 99%

VLSI implementation of real-time parallel DCT/DST lattice structures for video communications

Chiu

Kolagotla²,

Liu³

et al. 1992

Workshop on VLSI Signal Processing

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.Abstract -The alternate use [l] of the discrete cosine transform (DCT) and the discrete sine transform (DST) can achieve higher data compression rates and less blocking effects in image processing. A parallel lattice structure that can dually generate the 1-D DCT and DST is proposed. This architecture is ideally suited for VLSI implementation because of its maldularity, regularity, and local interconnections. The VLSI implementation of the lattice module using the distributed arithmetic approach is described. This realization of the lattice module using 2pm double metal CMOS technology is capable of processing a t a data rate of 116Mb/s in rea 1-time.

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“…A lot of research has been devoted to reduce the complexity of the DCT by reducing the number of multiplications and/or additions involved [8][9][10]. Such reduction in complexity is possible due to the use of the separability property of the DCT, where the 2D-DCT can be calculated using L 1D-DCTs operating on the rows of the L × L Block, followed by another L 1D-DCTs operating on the columns of the resulting coefficients of the first stage.…”

Section: Introductionmentioning

confidence: 99%

“…Another important DCT algorithm is based on the distributed arithmetic concept, combined with bit-serial/bit-parallel input data structures. Even though this algorithm generates a multiplier free algorithm but it uses extensive amount of memory which grows exponentially with the increase in the number of inputs [10]. A new modified algorithm based on the distributed arithmetic concept, NEDA, is published in [6] where coefficients are distributed instead of the inputs to solve the memory bottleneck.…”

Section: Introductionmentioning

confidence: 99%

Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures

Darwish

Bayoumi

2005

J VLSI Sign Process Syst Sign Image Video Technol

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An energy aware DCT (Discrete Cosine Transform) architecture based on the distributed arithmetic concept is proposed. Architectures based on the distributed arithmetic concept are inherently low power as they are multiplication free algorithms. One characteristic of the DCT is that upon transformation signal energies are concentrated in only a few coefficients (less than 25%) with the rest (75%) of the coefficients being insignificant and negligible. One can skip the computation of these terms without seriously affecting the output signal quality. Exploiting this idea, we propose a low energy DCT architecture that can achieve 55% savings in the energy dissipation and 28 db in signal quality. In addition, we propose an adaptive energy aware DCT architecture that trades off energy consumption for signal quality. Using this adaptive architecture, we present a study of the effect of coefficient elimination on energy consumption and signal quality.

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VLSI implementation of a 16*16 discrete cosine transform

Cited by 180 publications

References 8 publications

A simple processor core design for DCT/IDCT

A simple processor core design for DCT/IDCT

VLSI implementation of real-time parallel DCT/DST lattice structures for video communications

Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures

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