VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic

Soderstrand, M.A.; Escott, R.A.

doi:10.1109/tcs.1986.1085824

Cited by 34 publications

(8 citation statements)

References 24 publications

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“…Let and be residues modulo of two integers and , as defined in (9) and (10). Then the residue of their sum modulo is…”

Section: Radix-modulo-additionmentioning

confidence: 99%

“…Soderstrand and Escott have proposed merging of RNS with the multiple-valued logic paradigm, aiming at the VLSI implementation of FIR filters. In their approach, the selection of the number of levels to represent multiple-valued logic signals is consistent with the modulus of operation, providing a natural representation for RNS [9]. Bases which include moduli of the form and have been widely used in RNS architectures, as they provide for low-complexity implementations [10].…”

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confidence: 99%

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Novel high-radix residue number system architectures

Paliouras¹,

Stouraitis

2000

IEEE Trans. Circuits Syst. II

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Novel radix-modulo-arithmetic units for residue number system (RNS)-based architectures are introduced in this paper. The proposed circuits are shown to require several times less area than previously reported architectures for particular moduli of operation, while also being preferable in the area time complexity sense. The complexity reduction is achieved by extending the carry-ignore property of modulo-2 operations to radices higher than two, which are not powers of two. The carry-ignore property is efficiently exploited by introducing simplified digit adders, instead of general radixadders. The proposed simplification of digit adders is possible, since the maximum values of certain intermediate digits produced in the architecture are found to be less than 1. Detailed area and time complexity models are derived for the arithmetic units. The proposed radixarchitectures include multipliers, adders, and merged multipliers-adders. In addition, efficient radixbinary-to-residue and residue-to-binary conversion techniques and architectures are introduced.

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“…Let and be residues modulo of two integers and , as defined in (9) and (10). Then the residue of their sum modulo is…”

Section: Radix-modulo-additionmentioning

confidence: 99%

mentioning

confidence: 99%

Novel high-radix residue number system architectures

Paliouras¹,

Stouraitis

2000

IEEE Trans. Circuits Syst. II

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“…Previous RNS-based filter designs [171, [25], [26] were mainly for one-dimensional filtering. The existing two- dimensional RNS filters [27], [28] are not single-chip implementations.…”

Section: The Filter Architecturementioning

confidence: 99%

A single-chip pipelined 2-D FIR filter using residue arithmetic

Shanbhag

Siferd

1991

IEEE J. Solid-State Circuits

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Presented in this paper are novel circuits and architecture for residue arithmetic. These circuits are aimed towards fast and area-efficient single-chip implementation of digital signal processors. This has been achieved by following an algorithmic approach as opposed to the conventional look-up table approach. As a result, substantial area savings have resulted. The circuits include the residue adder, residue multiplier, binary-to-residue converter, and residue-to-binary converter. Based on these circuits, a prototype single-chip, 3 X3, finite impulse response (FIR), variable coefficient, linear-phase filter has been designed and fabricated in standard 2-pm CMOS technology. The filter has a pipelined architecture to increase the throughput. Testability in the form of scan-path registers has been incorporated. An interesting feature of this unique combination of residue arithmetic and scan-path testing is the possible trade-off available between the precision of the filter coefficients and the image data. The chip has a die size of 6.6 X4.2 mm', dissipates 220 mW of power, and is synchronized with a 180-11s clock cycle.

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“…The first MVL-RNS system was introduced by Soderstrand et al [5] to design a high speed FIR digital filter. Also, in [6], new RNS systems based on the moduli of forms r a , r b -1 and r c +1 are presented.…”

Section: Introductionmentioning

confidence: 99%

Efficient forward and reverse converters for a new high-radix moduli set

Molahosseini

Navi

Rafsanjani

2008

2008 International Symposium on Information Technology

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The residue number system (RNS) is a carry-free number system which can support parallel and highspeed arithmetic. In this paper, efficient and simple designs of forward and reverse converters for the new radix-r moduli set {r 2n , r n -1} are presented. This moduli set contains well-formed moduli which can result in fast RNS arithmetic and efficient forward and reverse conversion. In comparison with the last work, the proposed designs achieve higher-speed and lowercost resulting in higher overall performance of the RNS system.

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VLSI implementation in multiple-valued logic of an FIR digital filter using residue number system arithmetic

Cited by 34 publications

References 24 publications

Novel high-radix residue number system architectures

Novel high-radix residue number system architectures

A single-chip pipelined 2-D FIR filter using residue arithmetic

Efficient forward and reverse converters for a new high-radix moduli set

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