VLSI Chip Interconnection Technology Using Stacked Solder Bumps

Matsui, Nobuyuki; Sasaki, S.; Ohsaki, T.

doi:10.1109/tchmt.1987.1134795

Cited by 35 publications

(5 citation statements)

References 7 publications

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“…However, the solder joints processed by the conventional solder bumping technologies take on the shape of a spherical segment. Several approaches have been taken to increase the standoff height and control the shape of solder joint connection [11]- [16]. However, some of these technologies are not easily implementable in a manufacturing environment and some of them have yet to prove their cost-effectiveness.…”

Section: Introductionmentioning

confidence: 99%

Effects of solder joint shape and height on thermal fatigue lifetime

Liu

Lü

2003

IEEE Trans. Comp. Packag. Technol.

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Solder joint thermal fatigue failure is a major concern for area array technologies such as flip chip and ball grid array technologies. Solder joint geometry is an important factor influencing thermal fatigue lifetime. In this paper, the effects of solder joint shape and height on thermal fatigue lifetime are studied. Solder joint fatigue lifetime was evaluated using accelerated temperate cycling and adhesion test. Scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), scanning acoustic microscopy (nondestructive evaluation) and optical microscopy were utilized to examine the integrity of the joint and to detect cracks and other defects before and during accelerated fatigue tests. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time.

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Section: Introductionmentioning

confidence: 99%

Effects of solder joint shape and height on thermal fatigue lifetime

Liu

Lü

2003

IEEE Trans. Comp. Packag. Technol.

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“…Mathematical calculations and finite element modelings have shown that the hourglassshaped solder [131] and stacked solder bump [132] also help to relax the stresses. The geometry of the joint helps to reduce the cyclic strain and thereby, enhances the solder joints performance.…”

Section: Thermo-mechanical Stresses and Its Failure Mechanismsmentioning

confidence: 99%

Flip chip joint-in-via architecture on flexible substrates with Au-Sn interdiffusion bonding

Lee¹

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Pad pitch on substrate has been identified as a difficult flip-chip, which makes it a challenge to keep up with the microelectronic packaging revolution. This study proposes a joint-in-via architecture to meet this challenge but this research is hindered by the flux residues of conventional soldering. This study conceptualises the joint-in-via architecture and develops a fluxless bonding technique with its mechanism and reliability uncovered.

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“…Laboratories have developed a technique using a polyimide sheet deposited with solder bumps as an additional bump layer to be stacked and reflowed on a bumped substrate (Matsui et al, 1987). Copper (Cu) is used as the wetting layer and Ti as the diffusion barrier in the polyimide substrate pads.…”

Section: Nippon Telegraph and Telephone (Ntt) Electrical Communicationsmentioning

confidence: 99%

Development of a flip-chip composite interconnection system

Wong¹

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I would like to express my heartfelt gratitude to Prof. John Pang for his guidance, mentorship and invaluable discussions throughout my research. I would like to acknowledge the Singapore Institute of Manufacturing Technology (SIMTech), A*STAR, for sponsoring this research and my special thanks Dr Lim Ser Yong for his constant encouragement. Throughout this research, I received great support from my colleagues from JTG, MMP, MTG and PMG. In particular, I would like to extend my greatest appreciation to Mr Fan Wei for assisting in the test instrumentation, Ms Lu Haijing in the plating evaluations, Dr Yi Ming in the FEM, Mr Cheng Chek Kweng in the assembly setup, Mr Paramasivam in sample preparations and Ms Ng Fern Lan in the SEM. This thesis is dedicated to my beloved wife, Gek Noi, for her unceasing love and devotion to me throughout my academic pursuit, and to my four lovely daughters, Jane, Sarah, Joann and Rayna, for constantly surrounding me with their joy and laughter.

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VLSI Chip Interconnection Technology Using Stacked Solder Bumps

Cited by 35 publications

References 7 publications

Effects of solder joint shape and height on thermal fatigue lifetime

Effects of solder joint shape and height on thermal fatigue lifetime

Flip chip joint-in-via architecture on flexible substrates with Au-Sn interdiffusion bonding

Development of a flip-chip composite interconnection system

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