VLSI architectures for metric normalization in the Viterbi algorithm

Shung, C.B.; Siegel, Paul H.; Ungerboeck, G.; Thapar, H.K.

doi:10.1109/icc.1990.117356

Cited by 81 publications

(19 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is clear that (13) can be viewed as an example for the path metric update at state in (15), and it also shows that the ACS computations of the incoming paths at each state are performed selectively by the survivor information of the th stage. This means that only if the survivor information of the th stage is "1," the ACS computations at th stage are performed.…”

Section: B Updating Of Path Metricsmentioning

confidence: 98%

“…In general, just as the Viterbi algorithm can be formulated as a matrix-vector computation [7], the path metric update here can be expressed as (15) where represents the path metric row vector of the th stage with elements, whose th element is denoted by , represents the adjacency matrix, whose th element is denoted by representing the composite branch metrics from state of stage to state of stage , and represents the ACS operation according to the likelihood criterion.…”

Section: B Updating Of Path Metricsmentioning

confidence: 99%

“…To avoid normalization, which costs additional circuits in hardware implementation and increases the processing time, the moduloarithmetic approach [15], [16] is adopted here. It is known that for the original radix-2 trellis, the Viterbi algorithm inherently bounds the maximum dynamic range of the path metric at each state as (16) where is the number of states and is the maximum branch metric.…”

Section: Modulo Arithmetic For Acsmentioning

confidence: 99%

“…, the matrix-vector ACS computation as given in (15) can be processed by the 256 256 adjacency matrix and the 1 256 path metric vector . In this design, the adjacency matrix is partitioned into four 256 64 submatrices, and the four submatrices along with the path metric vector are used in (15) to update the corresponding path metrics of a given stage.…”

Section: ) Adjacency Matrix Partitioning and Time Multiplexing: Formentioning

confidence: 99%

See 3 more Smart Citations

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.Index Terms-Adaptive Viterbi decoder, field-programmable gate array (FPGA) implementation, low-power design, systolic array architecture.

show abstract

Section: B Updating Of Path Metricsmentioning

confidence: 98%

Section: B Updating Of Path Metricsmentioning

confidence: 99%

Section: Modulo Arithmetic For Acsmentioning

confidence: 99%

Section: ) Adjacency Matrix Partitioning and Time Multiplexing: Formentioning

confidence: 99%

See 2 more Smart Citations

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Guo

Ahmad

Swamy

et al. 2005

IEEE Trans. Circuits Syst. I

View full text Add to dashboard Cite

show abstract

“…The comparison in the ACS unit is implemented with the modified comparison rule [7]. Channel symbol wordlength is q = 3 since this gives negligible degradation in decoding performance compared to infinite precision.…”

Section: Implementation and Synthesis Resultsmentioning

confidence: 99%

Area and Power Efficient Trellis Computational Blocks in 0.13μm CMOS

Kamuf¹,

Öwall²,

Anderson³

2005 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Abstract-Improved add-compare-select and branch metric units are presented to reduce the complexity in the implementation of trellis-based decoding architectures. These units use a complementary property of the best rate 1/2 convolutional codes to reduce both area requirements and power consumption in a silicon implementation with no loss in decoding performance. For a 0.13µm CMOS process, synthesized computational blocks for decoders that can process codes from memory 2 up to 7 show up to 17% savings in both cell area and power consumption.

show abstract

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency

Broich

Noll

2016

J Sign Process Syst

View full text Add to dashboard Cite

VLSI architectures for metric normalization in the Viterbi algorithm

Cited by 81 publications

References 5 publications

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Area and Power Efficient Trellis Computational Blocks in 0.13μm CMOS

Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency

Contact Info

Product

Resources

About