FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

Abstract

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.Index Terms-Adaptive Viterbi decoder, field-programmable gate array (FPGA) implementation, low-power design, systolic array architecture.

The Design of Efficient Viterbi Decoder and Realization by FPGA

“…The result into the plus selection circuit, the comparison and selection circuit receives the selected path to leave, this information is fed to the path register. When the path register is in a 64 state path metric is equal when, after large number decision circuit outputs the decoded information, into the lower bit error monitoring and self synchronization circuit (Guo, Ahmad, & Swamay, 2005;Hsu, Kuo, & Hsu, 2007).…”