VLSI Architecture Based on Packet Data Transfer Scheme and Its Application

Homma, Yoshio; Kameyama, Michitaka; Fujioka, Yoshichika; Tomabechi, Nobuhiro

doi:10.1109/iscas.2005.1464955

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…In the proposed NoC architecture [4] the micronetwork is constructed using double transmission lines (left→right and right→left) and routers, as shown in Fig. 1.…”

Section: Noc Architecturementioning

confidence: 99%

Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

Munirul

Hasegawa

Kameyama

2006

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

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This paper presents an evaluation of multiple-valued packet multiplexing scheme for a Network-on-Chip (NoC) architecture. In the NoC architecture, data is transferred from one Processing Element (PE) to another PE through the routers in the form of a packet. A router, suitable for both the binary and the multiple-valued packets, is constructed using the Multiple Valued Source-Coupled Logic circuits. A packet is composed of flag, destination PE address and data fields. In the NoC architecture, packets are generated by microprogram control. In the proposed scheme, two binary packets are multiplexed if the destination PE addresses are the same. Based on address matching, packets are transferred from a source PE to a destination PE autonomously. As a result, the total number of packets can be reduced. The router is designed using 0.18μm CMOS design rule. HSPICE simulation results show that the delay of the router is significantly small for high speed packet transfer. Reduction of microprogram control storage is remarkable in the proposed scheme, because the data transfer can be done autonomously. The advantage is evaluated by simple analysis, and comparison with a conventional pipelined bus architecture is done.

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“…In the proposed NoC architecture [4] the micronetwork is constructed using double transmission lines (left→right and right→left) and routers, as shown in Fig. 1.…”

Section: Noc Architecturementioning

confidence: 99%

Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture

Munirul

Hasegawa

Kameyama

2006

36th International Symposium on Multiple-Valued Logic (ISMVL'06)

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“…In the packet data transfer, a router provided in each cell determines whether a packet is sent to the cell or the adjacent router. Simple data transfer control and flexible programming of logical interconnections can be achieved by the scheme [4].…”

Section: Introductionmentioning

confidence: 99%

Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation

Ito

Kameyama

2007

37th International Symposium on Multiple-Valued Logic (ISMVL'07)

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In the next-generation VLSI, it is desired to achieve ultimate flexibility and a high-performance low-power operation equivalent to that of a full-custom VLSI. In this paper, a reconfigurable VLSI which realizes a high-performance sequential logic circuit based on a bit-serial operation is proposed. A universal sequential logic module (USLM) suitable for local data transfer in a programmed sequential logic circuit is presented. A redundant multiple-valued sequential logic operation is also proposed, where linear summation of time-by-time adjacent bits is fully utilized to increase the input/output throughput of a sequential logic circuit. Moreover, packet data transfer scheme is introduced to make programmable interconnection possible in the bit-serial data transfer between cells composed of the multiple USLMs.

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