VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip

Bortolotti, Daniele; Pinto, Christian; Marongiu, Andrea; Ruggiero, Martino; Benini, Luca

doi:10.1109/ipdpsw.2013.177

Cited by 34 publications

(30 citation statements)

References 10 publications

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“…It can achieve up to 2 MIPS simulation performance with at most 25% error. VirtualSoC [53] is a method for the full system simulation of a general purpose CPU and a many-core hardware accelerator using Quick Emulator (QEMU) and SystemC. Virtual system-based approaches have been proposed by [54,55].…”

Section: Related Work On Efficiency Simulationsmentioning

confidence: 99%

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

et al. 2018

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Abstract:The threat of quantum-computer-assisted cryptanalysis is forcing the security community to develop new types of security protocols. These solutions must be secure against classical and post-quantum cryptanalysis techniques as well as feasible for all kinds of devices, including energy-restricted Internet of Things (IoT) devices. The quantum immunity can be implemented in the cryptographic layer, e.g., by using recent lattice-based key exchange algorithms NewHope or Frodo, or in the physical layer of wireless communication, by utilizing eavesdropping-resistant secrecy coding techniques. In this study, we explore and compare the feasibility and energy efficiency of selected cryptographic layer and physical layer approaches by applying an evaluation approach that is based on simulation and modeling. In particular, we consider NewHope and Frodo key exchange algorithms as well as novel physical layer secrecy coding approach that is based on polar codes. The results reveal that our proposed physical layer implementation is very competitive with respect to the cryptographic solutions, particularly in short-range wireless communication. We also observed that the total energy consumption is unequally divided between transmitting and receiving devices in all the studied approaches. This may be an advantage when designing security architectures for energy-restricted devices.

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Section: Related Work On Efficiency Simulationsmentioning

confidence: 99%

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

et al. 2018

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“…EXPERIMENTAL SETUP To evaluate the proposed approach using the DREAM technique, in terms of correction capabilities and power consumption, we model the architecture of the biomedical computing device INYU [12] by extending VirtualSOC [13], an existing multi-processor cycle-accurate architectural simulator. It can instantiate up to 16 ARM V6 cores with local and shared memories, accessed at a clock frequency of 200 MHz.…”

Section: B Read Operating Modementioning

confidence: 99%

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

Duch

Valle

Ganapathy

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-State-of-the-art wearable devices such as embedded biomedical monitoring systems apply voltage scaling to lower as much as possible their energy consumption and achieve longer battery lifetimes. While embedded memories often rely on Error Correction Codes (ECC) for error protection, in this paper we explore how the characteristics of biomedical applications can be exploited to develop new techniques with lower power overhead. We then introduce the Dynamic eRror compEnsation And Masking (DREAM) technique, that provides partial memory protection with less area and power overheads than ECC. Different tradeoffs between the error correction ability of the techniques and their energy consumption are examined to conclude that, when properly applied, DREAM consumes 21% less energy than a traditional ECC with Single Error Correction and Double Error Detection (SEC/DED) capabilities.

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“…Numerous heterogeneous architectures can be created with the combination of application-specific functional units, general purpose microprocessors, and FPGA resources [8][9][10][11]. The different solutions enable a trade-off between flexibility and computation performance.…”

Section: System On Chip Implementationsmentioning

confidence: 99%

A proposed synthesis method for Application-Specific Instruction Set Processors

Horváth

Hosszú

Kovács

2015

Microelectronics Journal

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a b s t r a c tDue to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a commonly used technique, but the automated hardware model generation is less frequently applied in terms of final RTL implementations. Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs. The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model. The proposed AMDL-based pre-synthesis method is based on a set of pre-defined VHDL implementation schemes, which ensure the qualities of the automatically generated register-transfer level models in terms of resource requirement and operation frequency. The design framework implementing the algorithms required by the synthesis method is also presented.

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VirtualSoC: A Full-System Simulation Environment for Massively Parallel Heterogeneous System-on-Chip

Cited by 34 publications

References 10 publications

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

Evaluating the Efficiency of Physical and Cryptographic Security Solutions for Quantum Immune IoT

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

A proposed synthesis method for Application-Specific Instruction Set Processors

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