Virtual wires: overcoming pin limitations in FPGA-based logic emulators

Babb, Jonathan; Tessier, Russell; Agarwal, Anant

doi:10.1109/fpga.1993.279469

Cited by 121 publications

(50 citation statements)

References 8 publications

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“…In other words, the FPGA is virtualized by multiplexing its physical components. The same idea [10] has also been followed for increasing the number of FPGA I/O pins, leading to the concept of virtual wires. In both cases the goal is to extend the capabilities of the FPGA devices.…”

Section: Specialized Virtual Fpga Structuresmentioning

confidence: 99%

Placing, Routing, and Editing Virtual FPGAs

Lagadec

Lavenier

Fabiani

et al. 2001

Field-Programmable Logic and Applications

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Abstract. This paper presents the benefits of using a generic FPGA tool set developed at the university of Brest for programming virtual FPGA structures. From a high level FPGA description, the basic FPGA tools such a placer, a router or an editor are automatically generated. The FPGA description is not constrained by any model, so that abstract FPGA structures, such as virtual FPGAs, can directly exploit the tool set as their basic programming tools.

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Section: Specialized Virtual Fpga Structuresmentioning

confidence: 99%

Placing, Routing, and Editing Virtual FPGAs

Lagadec

Lavenier

Fabiani

et al. 2001

Field-Programmable Logic and Applications

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“…We use VPR [14] to route inter-FPGA communication and estimate the minimum FPGAs required for an IO-limited mapping in Table III (Column Fully-Spatial). We can reduce cost at the expense of performance by serializing communication over external IO [15] (see Column Virtual-Wires in Table III). Both cases still require multiple FPGAs for the large Model-Evaluation graphs.…”

Section: Multi-fpga Designsmentioning

confidence: 99%

Accelerating SPICE Model-Evaluation using FPGAs

Kapre

DeHon

2009

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

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Abstract-Single-FPGA spatial implementations can provide an order of magnitude speedup over sequential microprocessor implementations for data-parallel, floating-point computation in SPICE model-evaluation. Model-evaluation is a key component of the SPICE circuit simulator and it is characterized by large irregular floating-point compute graphs. We show how to exploit the parallelism available in these graphs on single-FPGA designs with a low-overhead VLIW-scheduled architecture. Our architecture uses spatial floating-point operators coupled to local high-bandwidth memories and interconnected by a time-shared network. We retime operation inputs in the model-evaluation to allow independent scheduling of computation and communication. With this approach, we demonstrate speedups of 2-18× over a dual-core 3GHz Intel Xeon 5160 when using a Xilinx Virtex 5 LX330T for a variety of SPICE device models.

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“…Contemporary systems contain up to hundreds of devices packaged on boards in a cardcage. Although prototyping speeds range from a few megaHertz to 20-30 MHz [9], parallel verification systems provide up to five orders of magnitude speedup [1] versus uniprocessor simulation. This speedup has remained roughly constant since increases in ASIC integration due to Moore's law have tracked capacity increases in verification system devices.…”

Section: A Related Workmentioning

confidence: 99%

Static scheduling of multidomain circuits for fast functional verification

Kudlugi

Tessier

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With the advent of system-on-a-chip design, many application specific integrated circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This design characteristic presents a significant challenge when these ASIC designs are mapped to parallel verification hardware such as parallel cycle-based simulators and logic emulators. In general, these systems require all computation and communication to be synchronized to a global system clock. As a result, the undefined relationship between design clocks can make it difficult to determine hold times for synchronous storage elements and causality relationships along reconvergent communication paths. This paper presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to parallel verification hardware. Through analysis, it is shown that this approach is scalable to an unlimited number of domains and supports increasingly large design sizes. To prove the effectiveness of the authors' approach, developed algorithms have been integrated into the compilation system for a commercial multi-FPGA logic emulation system. For three designs mapped to a logic emulator using this software environment, modeling fidelity is maintained and performance is enhanced versus previous manual mapping approaches. A theoretical analysis based on Rent's rule validates the scalability of the approach as device sizes increase.

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Virtual wires: overcoming pin limitations in FPGA-based logic emulators

Cited by 121 publications

References 8 publications

Placing, Routing, and Editing Virtual FPGAs

Placing, Routing, and Editing Virtual FPGAs

Accelerating SPICE Model-Evaluation using FPGAs

Static scheduling of multidomain circuits for fast functional verification

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