Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits

Zhang, Wangyang; Li, Xin; Liu, F.; Acar, Erdem; Rutenbar, Rob A.; Blanton, R. D.

doi:10.1109/tcad.2011.2164536

Cited by 61 publications

(32 citation statements)

References 26 publications

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“…3 does not show high frequency components except the sampling locations. This is because we use a technique proposed in [15] that fills zeros in high-frequency DCT coefficients in order to recover the wafer maps with a very small number of samples. This wafer contains many dies, so without the technique, a more number of samples are required to recover the wafer maps accurately.…”

Section: Resultsmentioning

confidence: 99%

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations

Chung

Kim

Yang

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Process variation models for variation tolerant designs are developed through expensive silicon characterization. This paper presents a low-cost variation characterization method that takes advantage of correlations between test items. The proposed method is based on compressed sensing (CS), a new innovative theory in signal processing and information theory, and we formulate the problem of accounting for the correlations in the form of standard CS problems, allowing us to leverage advances in CS theory. We consider wafer-level measurement results for multiple test items a 3-D signal and propose the sparsifying transform that combines the 2-D discrete cosine transform and the Karhunen-Loéve transform. Our experimental results show that the proposed method reduces the number of samples required for the same accuracy up to 2X compared to virtual probe when two test items are used. IndexTerms-Approximate computing, compressed sensing (CS), intertest-item correlations, VLSI design.

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Section: Resultsmentioning

confidence: 99%

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations

Chung

Kim

Yang

2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Note that the expression in (19) does not rely on any approximation. Hence, it results in the exact solution of α t,m except for numerical errors.…”

Section: Fast Numerical Solvermentioning

confidence: 99%

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Zhang

Blanton

et al. 2014

2014 International Test Conference

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In this paper, a novel Bayesian model fusion (BMF) method is proposed for test cost reduction based on waferlevel spatial variation modeling. BMF relies on the assumption that a large number of wafers of the same circuit design (e.g., all wafers from the same lot) share a similar spatial pattern. Hence, the measurement data from one wafer can be borrowed to model the spatial variation of other wafers via Bayesian inference. By applying the Sherman-Morrison-Woodbury formula, a fast numerical algorithm is derived to reduce the computational cost of BMF for practical test applications. Furthermore, a new test methodology is developed based on BMF and it closely monitors the escape rate and yield loss. As is demonstrated by the wafer probe measurement data of an industrial RF transceiver, BMF achieves 1.125× reduction in test cost and 2.6× reduction in yield loss, compared to the conventional approach based on virtual probe (VP).

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“…The core modeling approach of Virtual Probe is a discrete cosine transform (DCT) that projects spatial statistics into the frequency domain. The main assumption of this approach is the spatial patterns of process variations are smooth and they can be represented by a few dominant DCT coefficients at low frequencies [10]. In this work, we employ Gaussian process models that perform a more general projection via kernel functions.…”

Section: Prior Workmentioning

confidence: 99%

Spatial estimation of wafer measurement parameters using Gaussian process models

Kupp

Huang

Carulli

et al. 2012

2012 IEEE International Test Conference

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In the course of semiconductor manufacturing, various e-test measurements (also known as inline or kerf measurements) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites, and include a variety of measurements that characterize the wafer's position in the process distribution. However, these measurements are often only used for wafer-level characterization by process and test teams, as the sampling can be quite sparse across the surface of the wafer. In this work, we introduce a novel methodology for extrapolating sparsely sampled e-test measurements to every die location on a wafer using Gaussian process models. Moreover, we introduce radial variation modeling to address variation along the wafer center-to-edge radius. The proposed methodology permits process and test engineers to examine e-test measurement outcomes at the die level, and makes no assumptions about wafer-towafer similarity or stationarity of process statistics over time. Using high volume manufacturing (HVM) data from industry, we demonstrate highly accurate cross-wafer spatial predictions of e-test measurements on more than 8,000 wafers.

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Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits

Cited by 61 publications

References 26 publications

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations

3-D Probe: Low-Cost Variation Modeling Using Intertest-Item Correlations

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling

Spatial estimation of wafer measurement parameters using Gaussian process models

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