2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) 2021
DOI: 10.1109/iemtronics52119.2021.9422547
|View full text |Cite
|
Sign up to set email alerts
|

Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
2
0

Year Published

2022
2022
2024
2024

Publication Types

Select...
5

Relationship

0
5

Authors

Journals

citations
Cited by 5 publications
(2 citation statements)
references
References 8 publications
0
2
0
Order By: Relevance
“…The advanced encryption standard (AES) algorithm is a symmetric encryption algorithm using keys of 128, 192 and 256 bits for AES-128 [23], AES-192, and AES-256 [51] block cipher respectively. Input plaintext data is 128 bits (16 Bytes) represented as a 4×4 column-major matrix.…”
Section: Encryption Using Advanced Encryption Standard Processmentioning
confidence: 99%
“…The advanced encryption standard (AES) algorithm is a symmetric encryption algorithm using keys of 128, 192 and 256 bits for AES-128 [23], AES-192, and AES-256 [51] block cipher respectively. Input plaintext data is 128 bits (16 Bytes) represented as a 4×4 column-major matrix.…”
Section: Encryption Using Advanced Encryption Standard Processmentioning
confidence: 99%
“…Therefore, ongoing research focuses on exploring avenues to enhance their optimization. Most prototype implementations use FPGAs as programmable fabric [8][9][10]. In addition, researchers have explored the integration of PQC on applicationspecific integrated circuits (ASIC) in various studies [11,12].…”
mentioning
confidence: 99%