Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches

Zhang, Michael; Asanović, Krste

doi:10.21236/ada466772

Cited by 29 publications

(40 citation statements)

References 37 publications

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“…Private cache based optimizations improve capacity utilization by controlling replication [13,27,138] and allowing capacity sharing between caches [27,156]. Shared cache based optimizations reduce on-chip latency by cache block migration [15,158], replication [159] or limiting the scope of sharing within a small cluster [68]. However the proposed solutions are either limited in only improving a certain class of workloads [13,15,138,156] or relying on specific cache or coherence protocol implementations [15,27,68,138,156,159].…”

Section: Latency Reduction Proposalsmentioning

confidence: 99%

“…In the context of CMP caching, flexible data placement is also needed to exploit the benefits of advanced cache replacement policies [57], reduce inter-thread conflict misses [158], provide QoS support via cache partitioning [81], and keep frequently accessed data close to the processor [26]. Highly associative caches (used by most CMP caching proposals) are thus needed to allow flexible data placement at the cost of extra area, latency, power and complexity overhead.…”

Section: Cache Replacement and Placementmentioning

confidence: 99%

“…Besides studies in CMP cache organizations [67,113,146], many hybrid caching schemes have been proposed to reduce the average memory access latency for CMPs [14,15,27,59,68,94,115,138,158,159].…”

Section: Cmp Caching Optimizations For Latency Reductionmentioning

confidence: 99%

“…Because VR keeps replicas in both the home node cache and all consumer caches, it can waste capacity when little data sharing exists (e.g., in multiprogrammed workloads). This issue was resolved by victim migration [158] via home block migration, implemented with extra shadow tags to keep track of the migrated data.…”

Section: Shared Cache Based Proposalsmentioning

confidence: 99%

“…Victim migration [158] CMP-NuRapid [27] NUCA substrate [68] OS-level page mapping [28] Interference A desirable CMP caching scheme should be able to simultaneously achieve multiple optimization goals, perform robustly for a wide range of workloads, while being amenable to simple and modular hardware implementations.…”

Section: Multithreaded Privatementioning

confidence: 99%

See 4 more Smart Citations

Cooperative Caching for Chip Multiprocessors

Chang¹,

Herrero²,

Canal³

et al. 2011

Cooperative Networking

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Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference.CC reduces the average memory access latency by balancing between cache latency and capacity optimizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a "shared" cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogrammed workloads.To isolate inter-thread caching interference, we add a time-sharing aspect on top of spatial cache partitioning. Our approach uses Multiple Time-sharing Partitions (MTP) to simultaneously improve throughput and fairness while maintaining QoS over the longer term. Each MTP partition unfairly improves at least one thread's throughput, and partitions favoring different threads are scheduled in a cooperative, timesharing manner to either maintain fairness and QoS, or implement priority. We also integrate MTP with CC's LRU-based capacity sharing policy to combine their benefits. The integrated scheme-Cooperative Caching Partitioning (CCP)-divides the total execution epochs into those controlled by either MTP or the ii baseline CC policy, respectively, according to the fraction of threads that can benefit from each of them. Our simulation results show that for a wide range of multiprogrammed workloads, CCP can improve throughput, fairness and QoS for workloads suffering from destructive interference, while achieving the performance benefit of the baseline CC policy for other workloads.iii

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Section: Latency Reduction Proposalsmentioning

confidence: 99%

Section: Cache Replacement and Placementmentioning

confidence: 99%

Section: Cmp Caching Optimizations For Latency Reductionmentioning

confidence: 99%

Section: Shared Cache Based Proposalsmentioning

confidence: 99%

Section: Multithreaded Privatementioning

confidence: 99%

See 3 more Smart Citations

Cooperative Caching for Chip Multiprocessors

Chang¹,

Herrero²,

Canal³

et al. 2011

Cooperative Networking

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ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Hammoud

Cho

Melhem

2009

High Performance Embedded Architectures and Compilers

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International audienceThis paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient shared cache design, the proposed scheme dynamically migrates cache blocks to cache banks that best minimize the average L2 access latency. Cache blocks are continuously monitored and the locations of the optimal corresponding cache banks are predicted to effectively alleviate the impact of non-uniform cache access latency. By adopting migration alone without replication, the exclusiveness of cache blocks is maintained, thus further optimizing the cache miss rate. Simulation results using a full system simulator demonstrate that the proposed controlled migration scheme outperforms the shared caching strategy and compares favorably with previously proposed replication schemes

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