ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Hammoud, Mohammad; Cho, Sangyeun; Melhem, Rami

doi:10.1007/978-3-540-92990-1_26

Cited by 14 publications

(16 citation statements)

References 21 publications

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“…This local cache of hosts is similar to the one proposed in [19] and we will refer to it as the local directory cache (LDC). Whenever Pi, receives a data block, bj , from a remote host node, L2m, m = i, the LDC at tile i adds an entry containing bj 's tag and the id of its host node, m. The next time Pi needs to access bj and misses in both its local L1 and L2 banks, the LDC is consulted and if an entry for bj existed, the data access request is sent directly to the cached host node, L2m, instead of through the directory.…”

Section: Maintaining Data Coherencementioning

confidence: 98%

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

Abousamra

Jones

Melhem

2011

Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers

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In chip multiprocessors (CMPs), data access latency depends on the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access latency is vital to achieving performance improvements and scalability of threaded applications. Multithreaded applications generally exhibit sharing of data among the program threads, which generates coherence and data traffic on the NoC.Many NoC designs exploit communication locality to reduce communication latency by configuring special fast paths on which communication is faster than the rest of the NoC. Communication patterns are directly affected by the cache organization. However, many cache organizations are designed in isolation of the underlying NoC or assume a simple NoC design, thus possibly missing optimization opportunities. In this work, we present a NoCaware cache design that creates a symbiotic relationship between the NoC and cache to reduce data access latency, improve utilization of cache capacity, and improve overall system performance. Specifically, considering a NoC designed to exploit communication locality, we design a Unique Private caching scheme that promotes locality in communication patterns. In turn, the NoC exploits this locality to allow fast access to remote data, thus reducing the need for data replication and allowing better utilization of cache capacity. The Unique Private cache stores the data mostly used by a processor core in its locally accessible cache bank, while leveraging dedicated high speed circuits in the interconnect to provide remote cores with fast access to shared data. Simulations of a suite of scientific and commercial workloads show that our proposed design achieves a speedup of 14% and 16% on a 16-core and a 64-core CMP, respectively, over the state-of-the-art NoC-Cache co-designed system which also exploits communication locality in multithreaded applications.

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Section: Maintaining Data Coherencementioning

confidence: 98%

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

Abousamra

Jones

Melhem

2011

Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers

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“…Based on this observation, they focused on minimizing the number of migrations with a placement mechanism that tries to place data in an optimal position. In the same vein, Hammoud et al [2009] predicted the optimal location of data by monitoring the behavior of programs. Finally, Chaudhuri [2009] proposed a coarse-grained data migration mechanism assisted by the operating system that monitors access patterns to decide where and when an entire page of data should be migrated.…”

Section: Related Workmentioning

confidence: 99%

“…Other migration schemes in the literature compute the optimal placement for a particular data block by taking into consideration dynamic parameters such as the usage of data or the processors that are currently sharing it [Hammoud et al 2009;Kandemir et al 2008]. An alternative for D-NUCA are those NUCA designs based on S-NUCA configurations Beckmann et al 2006;Hardavellas et al 2009].…”

Section: Introductionmentioning

confidence: 99%

The migration prefetcher

Lira

Jones

Molina

et al. 2012

ACM Trans. Archit. Code Optim.

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The exponential increase in multicore processor (CMP) cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Architecture (NUCA) designs have been proposed to address this problem. A NUCA divides the whole cache memory into smaller banks and allows banks nearer a processor core to have lower access latencies than those further away, thus mitigating the effects of the cache's internal wires. Determining the best placement for data in the NUCA cache at any particular moment during program execution is crucial for exploiting the benefits that this architecture provides. Dynamic NUCA (D-NUCA) allows data to be mapped to multiple banks within the NUCA cache, and then uses data migration to adapt data placement to the program's behavior. Although the standard migration scheme is effective in moving data to its optimal position within the cache, half the hits still occur within non-optimal banks. This paper reduces this number by anticipating data migrations and moving data to the optimal banks in advance of being required. We introduce a prefetcher component to the NUCA cache that predicts the next memory request based on the past. We develop a realistic implementation of this prefetcher and, furthermore, experiment with a perfect prefetcher that always knows where the data resides, in order to evaluate the limits of this approach. We show that using our realistic data prefetching to anticipate data migrations in the NUCA cache can reduce the access latency by 15% on average and achieve performance improvements of up to 17%.

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“…Hammoud et al proposed an adaptive migration policy for LLC management of CMPs [8] without replications. Jin et al [15] advocated the use of OS to control cache placement in a shared NUCA cache, suggesting that limited replication is possible through this approach.…”

Section: Related Workmentioning

confidence: 99%

High performance cache block replication using re-reference probability in CMPs

Wang

et al. 2011

2011 18th International Conference on High Performance Computing

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In a Chip Multiprocessor(CMP) with shared caches, the last level cache (LLC) is distributed across all the cores. This increases the on-chip communication delay and thus influence the processor's performance. The LLC is also quite inefficient due to plenty of dead blocks. Replication can be provided in shared caches by replicating cache blocks evicted from cores to the local LLC slices to minimize access latency through utilizing the cache space of dead blocks which will not be referenced again before they are evicted. However, naively allowing all evicted blocks to be replicated have limited performance benefit as such replicating does not take into account reuse probability of replicated blocks.This paper proposes Adaptive Probability Replication (APR), a mechanism that counts each block's accesses in L2 cache slices, and monitors the number of evicted blocks with different number of accesses, to estimate the Re-Reference Probability of blocks in their lifetime at runtime. Using predicted re-reference probability, APR adopts probability replication policy and probability insertion policy to replicate blocks at corresponding probabilities, and insert them at appropriate position, according to their re-reference probability. We evaluate APR for a 16-core tiled CMP using splash-2 and parsec benchmarks. APR improves performance by 21% on average compared to conventional shared cache design, by 17% over Victim Replication (VR), by 10% over Adaptive Selective Replication (ASR), and by 15% over Reactive NUCA (R-NUCA). The additional hardware cost of APR is well under 1% of L2 cache slice.

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ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors

Cited by 14 publications

References 21 publications

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

NoC-aware cache design for multithreaded execution on tiled chip multiprocessors

The migration prefetcher

High performance cache block replication using re-reference probability in CMPs

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