VHDL generator for a high performance convolutional neural network FPGA-based accelerator

Hamdan, Muhammad K.A.; Rover, Diane T.

doi:10.1109/reconfig.2017.8279827

Cited by 12 publications

(5 citation statements)

References 8 publications

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“…With the development of deep learning, the CNN model structure has become more and more complex, and it has become very difficult to conduct rapid validation and hardware-accelerated calculation for the model; at this stage, FPGA has come into the sight of AI scientists. Seeking new CNN hardware acceleration solutions has gradually become a hot topic in the field of AI [16][17][18]. More and more deep learning models use accelerators based on FPGAs.…”

Section: Related Workmentioning

confidence: 99%

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

Zheng

2022

Applied Sciences

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In recent years, the continuous development of artificial intelligence has largely been driven by algorithms and computing power. This paper mainly discusses the training and inference methods of artificial intelligence from the perspective of computing power. To address the issue of computing power, it is necessary to consider performance, cost, power consumption, flexibility, and robustness comprehensively. At present, the training of artificial intelligence models mostly are based on GPU platforms. Although GPUs offer high computing performance, their power consumption and cost are relatively high. It is not suitable to use GPUs as the implementation platform in certain application scenarios with demanding power consumption and cost. The emergence of high-performance heterogeneous architecture devices provides a new path for the integration of artificial intelligence training and inference. Typically, in Xilinx and Intel’s multi-core heterogeneous architecture, multiple high-performance processors and FPGAs are integrated into a single chip. When compared with the current separate training and inference method, heterogeneous architectures leverage a single chip to realize the integration of AI training and inference, providing a good balance of training and inference of different targets, further reducing the cost of training and implementation of AI inference and power consumption, so as to achieve the lightweight goals of computation, and to improve the flexibility and robustness of the system. In this paper, based on the LeNet-5 network structure, we first introduced the process of network training using a multi-core CPU in Xilinx’s latest multi-core heterogeneous architecture device, MPSoC. Then, the method of converting the network model into hardware logic implementation was studied, and the model parameters were transferred from the processing system of the device to the hardware accelerator structure, composed of programmable logic through the bus interface AXI provided on the chip. Finally, the integrated implementation method was tested and verified in Xilinx MPSoC. According to the test results, the recognition accuracy of this lightweight deployment scheme on MNIST dataset and CIFAR-10 dataset reached 99.5 and 75.4% respectively, while the average processing time of the single frame was only 2.2 ms. In addition, the power consumption of the network within the SoC hardware accelerator is only 1.363 W at 100 MHz.

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Section: Related Workmentioning

confidence: 99%

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

Zheng

2022

Applied Sciences

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“…This last approach is gaining popularity as it fully abstracts the details of the ANN away from the user. Other examples include [23]- [27], which propose easy to use frameworks to generate ANNs. Nevertheless, to have a parameterizable ready-to-use IP is convenient.…”

Section: Related Workmentioning

confidence: 99%

VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks

Aledo

Schafer

Moreno

2019

IEICE Trans. Inf. & Syst.

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This paper describes the advantages and disadvantages observed when describing complex parameterizable Artificial Neural Networks (ANNs) at the behavioral level using SystemC and at the Register Transfer Level (RTL) using VHDL. ANNs are complex to parameterize because they have a configurable number of layers, and each one of them has a unique configuration. This kind of structure makes ANNs, a priori, challenging to parameterize using Hardware Description Languages (HDL). Thus, it seems intuitively that ANNs would benefit from the raise in level of abstraction from RTL to behavioral level. This paper presents the results of implementing an ANN using both levels of abstractions. Results surprisingly show that VHDL leads to better results and allows a much higher degree of parameterization than SystemC. The implementation of these parameterizable ANNs are made open source and are freely available online. Finally, at the end of the paper we make some recommendation for future HLS tools to improve their parameterization capabilities. key words: VHDL, SystemC, high-level synthesis (HLS), artificial neural network (ANN)

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“…Evrişimsel Sinir Ağı (ESA) modeli, derin öğrenme algoritmalarının yaygın olarak kullanılan bir çeşididir. Bu ağların işlem performansını artırmak için uygulamaya yönelik devre tasarımları son yıllarda oldukça ilgi çekmektedir [2][3][4]. Gerçek zamanlı sınıflandırma [5], hedef tespiti [6], bilgisayar destekli teşhis koyma [7], nesne algılama [8], konuşma tanıma [9], yüz tanıma [10] gibi pek çok alanda kullanılan donanım tasarımları yapılmaktadır.…”

Section: Introductionunclassified

Evrişimli Sinir Ağları için Maksimum Ortaklama Devre Tasarımları

Bülbül

Gök

2020

Çukurova Üniversitesi Mühendislik-Mimarlık Fakültesi Dergisi

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Derin Öğrenme uygulamaları hızla gelişmekte özellikle de mobil cihazlarda yaygın olarak kullanılmaktadır. Bu platformlardaki mevcut performans, güç ve alan kısıtları, uygulamaya özgü donanım tasarımlarına ihtiyacı artırmaktadır. Görüntü işleme alanındaki en güncel yöntemlerden başlıcası Evrişimli Sinir Ağları'dır. Bu çalışmada gelişkin Evrişimli Sinir Ağı mimarilerinin önemli bir işlem bloğu olan maksimum ortaklama ünite tasarımları sunulmuştur. Maksimum-ortaklama katmanı Evrişimli Sinir Ağı tasarımlarının kritik gecikme yolunda olup, boru hatlı bir tümleşik devrenin ana çevrim hızını etki edebilecek önemdedir. Önerilen tasarımların toplam çerçeve işleme süreleri Standart Tasarıma göre çok daha kısadır. Önerilen tasarımlar farklı boru hatlı yapılara entegre edilebilecektir. Tasarımlar VHDL ile modellenmiş ve güncel bir FPGA platformu üzerinde sentezlenmiştir. Sentez sonuçları, önerilen tasarımların en hızlısının Standart Tasarımla karşılaştırıldığında 128x128'lik bir çerçeveyi yaklaşık 8,1 kat daha hızlı işlediğini göstermiştir.

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VHDL generator for a high performance convolutional neural network FPGA-based accelerator

Cited by 12 publications

References 8 publications

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

Research on the Lightweight Deployment Method of Integration of Training and Inference in Artificial Intelligence

VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks

Evrişimli Sinir Ağları için Maksimum Ortaklama Devre Tasarımları

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