VHD/sub e/LDO: A new mixed mode simulation

Tahawy, H. El; Rodriguez, D.; Garcia-Sabiro, S.; Mayol, J.-J.

doi:10.1109/eurdac.1993.410690

Cited by 9 publications

(3 citation statements)

References 3 publications

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“…As selfadvancing processes have high internal communication demands, this communication is kept local. Tahawy et al [47] were the first to investigate synchronization of processes for mixed-mode simulation. However, the process synchronization scheme introduced by Tahawy only considered sequential event-driven simulation kernels.…”

Section: Extending Parallel Logic Simulation To Mixed-technology Simumentioning

confidence: 99%

Analysis and Simulation of Mixed-Technology VLSI Systems

Martin

Radhakrishnan

Rao

et al. 2002

Journal of Parallel and Distributed Computing

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Section: Extending Parallel Logic Simulation To Mixed-technology Simumentioning

confidence: 99%

Analysis and Simulation of Mixed-Technology VLSI Systems

Martin

Radhakrishnan

Rao

et al. 2002

Journal of Parallel and Distributed Computing

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“…A single unified simulation framework for the simulation of AMS designs using two parallel stand alone simulators (Xyce for SPICE, SAVANT for VHDL) designed for high performance simulation in their respective solution spaces was described in [2]. Another mixed-domain simulation framework was proposed in [3] based on VHDL and ELDO. The commercial tool Nexus-PDK [4] supports co-simulation of cycle accurate C/C++ with SystemC, MATLAB/Simulink, and VHDL/Verilog simulators.…”

Section: Introductionmentioning

confidence: 99%

On the simulation performance of contemporary AMS hardware description languages

Narayanan

Abbasi

Zaki

et al. 2008

2008 International Conference on Microelectronics

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Mixed-Signal extensions to VHDL, Verilog, and SystemC languages have been developed in order to provide a unifying environment for the modeling and verification of Analog and Mixed Signal (AMS) designs at different levels of abstraction. In this paper, we model the behavior of a set of benchmark designs in VHDL-AMS, Verilog-AMS and SystemC-AMS and compare the simulation performance with HSPICE. The various experimental results observed for the benchmark circuits show the superiority of VHDL-AMS and Verilog-AMS against SystemC-AMS and HSPICE in terms of simulation runtimes at lower level of abstraction.

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“…Tahawy et al [13] was the first to investigate synchronization of processes for mixed-mode simulation. However, the process synchronization scheme introduced by Tahawy only considered sequential event-driven simulation kernels with a single self advancing process.…”

Section: Background and Related Workmentioning

confidence: 99%

Parallel mixed-technology simulation

Frey¹,

Radhakrishnan²

Proceedings Fourteenth Workshop on Parallel and Distributed Simulation

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Circuit simulation has proven to be one of the most important computer aided design (CAD) methods for the analysis and validation of integrated circuit designs. A popular approach to describing circuits for simulation purposes is to use a hardware description language such as VHDL. Similar efforts have also been carried out in the analog domain that has led to tools such as SPICE. However, with the growing trend of hardware designs that contain both analog and digital components, design environments that seamlessly integrate analog and digital circuitry are needed. Simulation of such circuits is however, exacerbated by the higher resource (CPU and memory) demands that arise when analog and digital models are integrated in a mixed-mode (analog and digital) simulation. One solution to this problem is to use PDES algorithms on a distributed platform. However, a synchronization interface between the analog and digital simulation environment is required to achieve integrated mixed-mode simulation. In this paper, we present the issues involved in the construction of synchronization protocols which support mixed-mode simulation in a distributed simulation environment. The proposed synchronization protocols provide an interface between an optimistic (Time Warp based) discrete-event simulation kernel and any continuous time simulation kernel. Empirical and formal analyses were conducted to ensure correctness and completeness of the protocols and the results of these analyses are also presented.0-7695-0677-1/00 $10.00 ã 2000 IEEE

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VHD/sub e/LDO: A new mixed mode simulation

Cited by 9 publications

References 3 publications

Analysis and Simulation of Mixed-Technology VLSI Systems

Analysis and Simulation of Mixed-Technology VLSI Systems

On the simulation performance of contemporary AMS hardware description languages

Parallel mixed-technology simulation

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