Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs

Khanshan, Tohid Moradi; Nematzade, Mojde; Hadidi, Khayrollah; Khoei, Abdollah; Koozehkanani, Ziaddin Daie; Sobhi, Jafar

doi:10.1007/s10470-016-0754-9

Cited by 5 publications

(5 citation statements)

References 11 publications

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“…Some techniques have been developed by many researchers to decrease hold error voltage in S/H circuit [12][13][14][15][16][17][18][19][20][21]. Most of them use an additional circuit to decrease the hold error.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…From equation 13it can be known that total hold error consists of two simple parts with a different sign, the width of P-type MOS transistor W P with a coefficient a and width of N-type MOS transistor W N with a coefficient -b. The coefficient a and b is shown in equations (14) and (15), respectively. These equations can now be used to adjust W P and W N properly to achieve zero hold error.…”

Section: Proposed Methodsmentioning

confidence: 99%

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A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Setiabudi

Tamura

Tanno

2018

International Journal on Advanced Science, Engineering and Information Technology

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Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N /W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

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Section: Proposed Methodsmentioning

confidence: 99%

Section: Proposed Methodsmentioning

confidence: 99%

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Setiabudi

Tamura

Tanno

2018

International Journal on Advanced Science, Engineering and Information Technology

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“…The other technique is bottom plate sampling. Recently, the improvement of bottom plate sampling is reported in [8,9]. This technique shows decent performance to decrease charge injection and clock feedthrough effect, but the complex clocking phase in this technique rises another problem in system complexity.…”

Section: Channel Charge Injection Clock Feedthrough and On-resistancmentioning

confidence: 99%

“…Based on the operation principles explanation, the output of NMOS and PMOS bootstrap circuits can be written in Eqs. (8) and 9, respectively.…”

Section: Proposed S/h Circuitmentioning

confidence: 99%

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High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

Setiabudi¹,

Tamura²,

Tanno³

2018

IJECE

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

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A New Low-Power Non-uniform Sample and Hold Circuit for Biomedical Signal Processing Applications

Bagher Nasrabadi,

Dolatshahi,

Zanjani

et al. 2024

Circuits Syst Signal Process

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Very linear open-loop CMOS sample-and-hold structure for high precision and high speed ADCs

Cited by 5 publications

References 11 publications

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

A New Low-Power Non-uniform Sample and Hold Circuit for Biomedical Signal Processing Applications

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