Vertically stacked SnSe homojunctions and negative capacitance for fast low-power tunneling transistors

Li, Hong; Liang, Jiakun; Xu, Peipei; Luo, Jing; Liu, Fengbin

doi:10.1039/d0ra03279d

Cited by 12 publications

(22 citation statements)

References 44 publications

(54 reference statements)

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“…This discovery is conducive to the practical application. [ 38 ] Various asymmetric N s / N d are considered for the BL source SnS homojunction TFET with L g = 10 nm. When the N s or N d decreases continuously from 5 × 10 13 to 0.3 × 10 13 cm −2 , I leak decreases accordingly from 4 × 10 −7 to 10 −8 –10 −10 µA µm −1 , as shown in Table 1 .…”

Section: Resultsmentioning

confidence: 99%

“…a) I on , b) τ , and c) PDP as a function of L g of the optimal sub‐10 nm BL source SnS homojunction n ‐TFETs and n ‐NCTFETs ( V dd = 0.64–0.74 V) compared with the ITRS requirements for LP devices and the vertical SnSe p ‐TFET and their p ‐NCTFET counterpart, [ 38 ] vertical BP p ‐TFET, [ 5 ] planar GeSe p ‐TFET, [ 22 ] and planar SnS p ‐TFET. [ 22 ] …”

Section: Resultsmentioning

confidence: 99%

“…Compared with the benchmarked 2D TFETs, the BL source SnS TFETs have a better τ than its planar SnS counterpart at L g = 10 nm and the vertical SnSe TFET at L g = 7 nm. [ 38 ]…”

Section: Resultsmentioning

confidence: 99%

“…As a result, I on of the NCTFETs with L g of 7 and 5 nm enhanced to 1052 and 783 µA µm −1 , respectively, which are about 5 and 20 times of their TFET counterparts, and surpass the ITRS targets of 337 and 295 µA µm −1 , respectively. Also, I on of the BL source SnS NCTFET is much higher than 346–565 µA µm −1 of the vertical SnSe NCTFETs with L g = 5–7 nm [ 38 ] (See Table 2 and Figure 2a). τ improves apparently to 0.183 and 0.225 ps, respectively, which are better than all the benchmarked 2D TFETs, while PDP becomes worse slightly to 0.127 and 0.114 fJ µm −1 , respectively, which are worse than all the benchmarked 2D TFETs.…”

Section: Resultsmentioning

confidence: 99%

“…The transfer characteristics of the BL source, BL source +OL, and SixL source SnS TFETs are given in Figure 1e,f), and very close I leak values are obtained. Benchmark of I on , τ, and PDP at I off = 10 −5 µA µm −1 of the three types of the SnS homojunction TFETs against those of the planar GeSe TFET, [ 22 ] planar BP TFET, [ 39 ] Sb TFET with 1 nm quad hetero, [ 39 ] and vertical SnSe TFET [ 38 ] are presented in Table 3 . Unfortunately, increasing the number of layers on the source and introducing an overlap region in the channel shows side effects on I on , τ , and PDP, which doesn't meet the expectations of improving the on‐state current like similar BP homojunction TFETs.…”

Section: Resultsmentioning

confidence: 99%

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Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

Liang

Liu

et al. 2021

Advcd Theory and Sims

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Utilizing the layer‐controlled bandgap of a 2D material is an effective way of improving a tunneling field‐effect transistor (TFET) device's performance because of the narrowing tunneling barrier. An ab initio quantum transport method is used to study the SnS homojunction TFETs at a sub‐10 nm scale through layer controlling. The optimal SnS homojunction TFET has a bilayer SnS as the source electrode, which possesses a low leakage current like the ML SnS TFET and a high on‐state current like the BL SnS TFET. The low SSave_4dec (subthreshold swing over four decades of the drain currents) of ≈47–48 mV dec−1 and I60 (drain current at 60 mV dec−1) of ≈1.1–1.2 µA µm−1 implies the BL source SnS TFET, a fast low‐power (LP) device. The optimal BL source SnS TFET with a gate length of Lg = 10 nm exceeds the LP device requirement of the International Technology Roadmap for Semiconductors (ITRS) (2013 version), and its negative capacitance counterparts can exceed the ITRS 2028 target for LP device at Lg = 5 nm.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

“…Compared with the benchmarked 2D TFETs, the BL source SnS TFETs have a better τ than its planar SnS counterpart at L g = 10 nm and the vertical SnSe TFET at L g = 7 nm. [ 38 ]…”

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

See 3 more Smart Citations

Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

Liang

Liu

et al. 2021

Advcd Theory and Sims

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Recent Advances in SnSe Nanostructures beyond Thermoelectricity

Wang

Huang

et al. 2022

Adv Funct Materials

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Layered SnSe is an emerging class of black phosphorus, which is non-toxic, eco-friendly, and chemically stable. Recently, SnSe nanostructures have triggered more research interest and enabled broad applications beyond demonstrating their great performances on thermoelectricity. However, there are also a great many significant studies of SnSe nanostructures beyond thermoelectricity. SnSe quantum dots, nanosheets, nanowires, and thin films with diverse morphologies have been synthesized using various chemical and physical preparation approaches. SnSe is a multi-phase semiconductor, and its nanostructures endow unique properties, including small electron effective mass, ultralow thermal conductivity, huge anisotropy, and the largest 2D piezoelectric coefficient ever predicted. The versatility of SnSe nanostructures can enable potential applications ranging from ultrafast photonics, logic devices, photodetectors, solar cells, photocatalysis, energy storage, and biology to more cutting-edge interdisciplinary subjects. In this review, the recent advances made in SnSe nanostructures are summarized, covering basics, synthesis, properties, and applications, just giving a passing comment on thermoelectricity. An in-depth perspective on the challenges and prospects of SnSe nanostructures toward broad and practical applications is also given.

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Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

Wang

et al. 2022

J Comput Electron

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Compared with a 2D homogeneous channel, the introduction of a 2D/2D homojunction or heterojunction is a promising method to promote the performance of a TFET mainly by controlling the tunneling barrier. We simulate the 10-nm-Lg double-gated GeSe homojunction TFETs and vdW GeSe/GeTe heterojunction TFETs using the ab initio quantum transport calculations. Two constructions are considered for both the homojunction and heterojunction TFETs by placing the BL GeSe and vdW GeSe/GeTe heterojunction as the source or drain while the channel and the remaining drain or source use ML GeSe. The on-state current (Ion) of the optimal n-type BL-ML GeSe source homojunction TFET and the optimal p-type vdW GeSe/GeTe drain heterojunction TFET are 2320 and 2387 μA μm -1 , respectively, which are 50% and 64% larger than Ion of the ML GeSe homogeneous TFET. Inspiringly, the device performances (Ion, intrinsic delay time τ, and power delay product PDP) of both the optimal ntype GeSe homojunction and p-type vdW GeSe/GeTe heterojunction TFETs meet the requirement of the International Roadmap for Device and Systems high-performance device for the year of 2034 (2020 version).

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Vertically stacked SnSe homojunctions and negative capacitance for fast low-power tunneling transistors

Abstract: The vertical SnSe homojunction TFETs and NCTFETs are potential candidates for fast low-power application.

Cited by 12 publications

References 44 publications

Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

Layer‐Controlled Low‐Power Tunneling Transistors Based on SnS Homojunction

Recent Advances in SnSe Nanostructures beyond Thermoelectricity

Device simulation of GeSe homojunction and vdW GeSe/GeTe heterojunction TFETs for high-performance application

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