Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

Kurita, Yasuo; Matsui, Satoshi; Takahashi, Nobuaki; Soejima, K.; Komuro, M.; Itou, M.; Kawano, Motoharu

doi:10.1109/tadvp.2009.2015461

Cited by 47 publications

(18 citation statements)

References 11 publications

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“…Here, due to the low capacitance and resistance values, 128 NAND flash memory dies can be stacked into a package with very small overhead compared with conventional wire-bondings. It is presented that by using poly-Si via-first processing technology, DRAM dies can be stacked with NAND flash dies without contamination, despite the fact that only 32 layers can be stacked because of higher resistance [11].…”

Section: Related Workmentioning

confidence: 99%

MMSoC

Liljeberg

Plosila

et al. 2013

Proceedings of the 14th International Conference on Computer Systems and Technologies

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In this paper, we propose a three dimensional storage-on-chip design that provides systems with high integration. The main memory and disk storage are stacked on-chip with through silicon vias. We analyse implementation feasibility, a 3D chip with multiple layers of DRAM and NAND storage is modelled accordingly. We use a sophisticated simulation toolset to analyse the performance of various architectures. Full system evaluation using SPLASH-2 benchmarks shows that, compared to conventional off-chip main memory and disk storage, our design can reduce the overall execution time by 38.3% on average.

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Section: Related Workmentioning

confidence: 99%

MMSoC

Liljeberg

Plosila

et al. 2013

Proceedings of the 14th International Conference on Computer Systems and Technologies

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“…During IEEE/ESTC2010 and ECTC2011, NEC (now Renesas) presented a couple of papers on system in wafer-level package (SiWLP) [19], and "RDL-first" FOWLP [20]. These papers are based on their SMArt chip connection with feed through interposer packaging technology for interchip wide-band data transfer [21,22] and 3D stacked memory integrated on logic devices [23][24][25][26][27]. The feed through interposer (FTI) used in SMArt chip connection with feed through interposer is a film with ultrafine linewidth and spacing RDLs.…”

Section: Introductionmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…The TSV technology, which is one of most focused 3D stacking technologies, has been extensively researched, because it could provide the shortest electrical interconnection to 3D stacked semiconductor device. [1][2][3][4] Especially, TSV filling process that fills the Cu in the TSV by the electrodeposition was quickly adopted, because this process was already utilized for the metal interconnection in VLSI and advanced memory devices.…”

Section: Introductionmentioning

confidence: 99%

Electrodeposition of Nanotwin Cu by Pulse Current for Through-Si-Via (TSV) Process

Jin¹,

Seo²,

Wang³

et al. 2016

j nanosci nanotechnol

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Recently, the through-Si-via (TSV) had been focused as an optimal solution for interconnecting the 3-dimensionaly stacked semiconductor devices. One of core processes in the TSV technology is the Cu filling process which electrochemically forms the Cu in the via with high aspect ratio. The nanotwin Cu is effective candidate for replacing the conventional electrodeposited Cu due to its ultrahigh mechanical strength and good electrical conductivity. In this work, the formation of the nanotwin Cu in the TSV by applying pulse current was systematically studied. Also, TSV filling behavior by electrodeposition with pulse current was compared with direct current. The variation of mechanical properties as well as the electrical resistivity of electrodeposited Cu by the pulse current also investigated.

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Vertical Integration of Stacked DRAM and High-Speed Logic Device Using SMAFTI Technology

Cited by 47 publications

References 11 publications

MMSoC

MMSoC

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Electrodeposition of Nanotwin Cu by Pulse Current for Through-Si-Via (TSV) Process

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