Vertical Inner Gate Transistors for 4F² DRAM Cell

Substrate-Dependent Growth Behavior of Atomic-Layer-Deposited Zinc Oxide and Zinc Tin Oxide Thin Films for Thin-Film Transistor Applications

“…However, the lack of holes, which are necessary for the erase operation, among other problems, could hinder their applications. Cell-level stacking of the memory cells could be the next viable direction for the higher density DRAM as the shrinking trend of minimum feature size in the planar-structured device will face a significant challenge at ∼10 nm technology node. , In this regard, the amorphous ZTO film could play a pivotal role in fabricating the stacked DRAM cells.…”

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

“…To validate the feasibility of the RC-FeMFET to 1T-DRAM, pulse program operations are investigated considering write recovery time (tWR) of DRAMs. Since the tWR of state-of-art DRAM cell transistors is about 15 ns, the program pulse width (tW) is set to 15 ns in this work [2,24,25]. Fig.…”

“…ne transistor dynamic random-access memory (1T-DRAM) has been extensively researched to overcome the scaling limitation of conventional one transistor-one capacitor (1T1C) DRAMs [1][2][3][4][5]. Especially, ferroelectric-gate field-effect transistors (FeFETs) have been considered as one of the strongest candidates because they are not only completely compatible with the fabrication process of existing DRAM cell transistors, but also fast program/erase speeds, a high on/off current ratio for stable read current sensing margin (RSM), and robust data retention are achievable [6,7].…”