Single-event transient characteristics of vertical gate-all-around junctionless field-effect transistor on bulk substrate

Yoon, Young Jun; Lee, Jae Sang; Kang, In Man; Kim, Dong-Seok

doi:10.1007/s00339-020-04250-6

Cited by 4 publications

(2 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An excellent anti-radiation performance has been achieved using an N-type TFET with a Si 1−x Ge x /Si hetero-junction in the ultra-shallow N+ pocket region 34 . The Vertical JLFET with the Ge source region obtained an improved radiation hardness 35 .…”

Section: Introductionmentioning

confidence: 99%

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Aishwarya,

Lakshmi

2024

Sci Rep

View full text Add to dashboard Cite

Semiconductor devices used in radiation environment are more prone to degradation in device performance. Junctionless Tunnel Field Effect Transistor (JLTFET) is one of the most potential candidates which overcomes the short channel effects and fabrication difficulties. In this work, 20 nm JLTFET is proposed with Silicon in the drain/channel region whereas source uses different materials, Silicon Germanium (SiGe), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Indium Arsenide (InAs). The device performance is examined by subjecting it to heavy ion radiation at a lower and higher dose of linear energy transfer (LET) values. It can be seen that the most sensitive location is the source/channel (S/C) interface for SiGe, GaN and GaAs whereas the drain/channel (D/C) interface for InAs. Further analysis is carried out at these vulnerable regions by matching ION of all materials. The parameters, transient peak current (Ipeak), collected charge (QC), threshold voltage shift (ΔVth) and bipolar gain (β) are extracted using transient simulations. It is observed that for a lower dose of LET, Ipeak of SiGe is 27% lesser than InAs and for higher dose of LET, SiGe shows 56% lesser Ipeak than InAs. SiGe is less sensitive at lower and higher dose of LET due to reduced ΔVth, tunneling and electron density.

show abstract

Section: Introductionmentioning

confidence: 99%

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Aishwarya,

Lakshmi

2024

Sci Rep

View full text Add to dashboard Cite

show abstract

“…The proposed DRAM memory cell has to be designed using SOI having a floating body effect in the body of the transistor. The concept of floating body effect on SOI generates piles of manufacturing of memory cells [7][8][9][10]. However, capacitorless memory cells can be formed using bulk and planer devices like NMOS, double gate junction-less transistors [11,12].…”

Section: Introductionmentioning

confidence: 99%

Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

Singh¹,

Dhar²,

Baishya³

2021

Phys. Scr.

View full text Add to dashboard Cite

This paper presents micro-features of capacitorless memory cells based on snapback phenomenon and modeling of space-charges. 2—Dimensional gate grounded NMOS structure is specified and its operational window of the memory cell is inspected using the Synopsys TCAD tool. This work examines snapback behaviour in one transistor DRAM memory cell in the absence of a storage capacitor under zero gate bias and applied ramp of high current at the drain terminal. Carrier electrostatics and memory cell mechanisms are also explored by adjusting the slope of the high current ramp. The process variation is examined for different parameters in the device. The current crowding phenomenon due to the injection of electrons and holes is investigated, giving rise to ambipolar behaviour. Due to the snapback, redistribution of electron and hole current is investigated. This work also evaluates the impact on electrostatic potential along channel and bulk under the snapback. It explains the dependency of snapback on potential build-up. Post-snapback electron current flipping presents the flow line near the gate region. The bipolar activity is manifested in surface and bulk regions to show its impact through analytics. The effect of gate biasing is also examined under the applied current ramp.

show abstract

Vertical 3D diamond field effect transistors with nanoscale gate-all-around

Sun

Guo

et al. 2022

Materials Science in Semiconductor Processing

View full text Add to dashboard Cite

Single-event transient characteristics of vertical gate-all-around junctionless field-effect transistor on bulk substrate

Cited by 4 publications

References 37 publications

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

TCAD simulation study of heavy ion radiation effects on hetero junctionless tunnel field effect transistor

Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

Vertical 3D diamond field effect transistors with nanoscale gate-all-around

Contact Info

Product

Resources

About