Vertical 40 nm Impact Ionization MOSFET (I-MOS) for high temperature applications

Abelein, Ulrich; Assmuth, Andreas; Iskra, P.; Reinl, M.; Schlosser, Michael; Sulima, T.; Eisele, I.

doi:10.1109/icmel.2008.4559280

Cited by 18 publications

(7 citation statements)

References 8 publications

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“…Figure 3 shows the comparison of transfer characteristic, I DS -V GS of VESIMOS-DP with different DP thickness. Figure 3 revealed that VESIMOS-DP works well for low V DS , which has overcome the problem faced by the conventional IMOS devices [8][9][10]. The energy of electrons required in the impact-ionization region is much lower compared to the lateral IMOS since the impact ionization is not the only mechanism contributing to the extremely fast rising drain current.…”

Section: Resultsmentioning

confidence: 93%

“…The holes generated by impact ionization acts as a base currents and drain source current increases as the current of the parasitic bipolar transistor (PBT) is switched on. This additional current amplification mechanism contributes to the lower subthreshold slope, but with a certain hysteresis [10] due to the PBT effect.…”

Section: Resultsmentioning

confidence: 97%

“…It shows excellent subthreshold slope of 4 mV/dec and suppress leakage current efficiently at high temp as well as a very good I ON /I OFF current ratio. Most importantly, it showed no hot carrier effects [10][11]. Hence, it was reliable.…”

Section: Introductionmentioning

confidence: 97%

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Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

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Section: Resultsmentioning

confidence: 93%

Section: Resultsmentioning

confidence: 97%

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Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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show abstract

“…In an attempt to reduce this voltage, the vertical IMOS, which is a planar-doped barrier MOSFET with a floating body, has been introduced and investigated extensively by experiments [29][30][31][32]. This vertical IMOS is not based on avalanche breakdown like the lateral IMOS.…”

Section: Introductionmentioning

confidence: 98%

“…In [31], a very good subthreshold slope of 1.06 mV/dec at V D = 2.25 V has been obtained. Moreover, this device offers the mechanisms for mitigating the damages from hot electrons almost completely [30] and shows the capability of working properly under high temperatures [32]. The device structure is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%