Investigation of the performance of strained-SiGe vertical IMOS-transistors

Dinh, Thanh Viet; Kraus, R.; Jungemann, Christoph

doi:10.1016/j.sse.2010.04.015

Cited by 17 publications

(5 citation statements)

References 43 publications

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“…This additional current amplification mechanism contributes to the lower subthreshold slope, but with a certain hysteresis [20] due to the PBT effect. PBT effect prevents the device from being able to switch off and the device will never undergoes breakdown state.…”

Section: Results Anmentioning

confidence: 99%

“…To bring the V DS even further down, the concept of strained Silicon Germanium (SiGe) in the vertical IMOS device was developed [20][21]. This compressive strain developed results in high carrier mobility, high impact ionization rates and better ON-OFF current ratios, besides retaining the good subthreshold slopes shown by vertical IMOS device [22][23][24].…”

Section: Introductionmentioning

confidence: 99%

“…This compressive strain developed results in high carrier mobility, high impact ionization rates and better ON-OFF current ratios, besides retaining the good subthreshold slopes shown by vertical IMOS device [22][23][24]. However, this device suffers low breakdown voltage and parasitic bipolar transistors (PBT) effect [25].…”

Section: Introductionmentioning

confidence: 99%

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Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Saad

Zuhir

Seng

et al. 2013

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. There are significant drop in subthreshold slope (S) while threshold voltage is increase as the body doping concentration increases. It is notable that for body doping concentration above 10 20 , the S values keep increasing which is not recommended as the switching speed getting higher distracting performance of the device. An improved stability of threshold voltage, V TH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. In addition, the output characteristic was also highlighted a very good drain current at different gate voltage with the increasing of drain voltage for VESIMOS-DP with high body doping concentration. VESIMOS-DP with low body doping concentration suffers PBT effect that prevents the device from being able to switch off. Hence, high body doping concentrations are imperative for obtaining better device characteristics and ensure the device works in II mode.

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Section: Results Anmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Saad

Zuhir

Seng

et al. 2013

RSM 2013 IEEE Regional Symposium on Micro and Nanoelectronics

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“…It showed both reduction in threshold voltage and supply voltage of about 0.7V. This compressive strain developed results in high carrier mobility, high impact ionization rates and better ON-OFF current ratios, besides retaining the good subthreshold slopes shown by vertical IMOS devices [14][15].…”

Section: Introductionmentioning

confidence: 94%

“…Hence, the concept of strained Silicon Germanium (SiGe) in the vertical IMOS device was developed [12][13]. It showed both reduction in threshold voltage and supply voltage of about 0.7V.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

Saad

Hamzah

Seng

et al. 2013

2013 Fifth International Conference on Computational Intelligence, Modelling and Simulation

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The Vertical Strained Silicon Germanium (SiGe) Impact Ionization MOSFET with Dielectric Pocket (VESIMOS-DP) has been successfully developed and analyzed in this paper. The comparison between VESIMOS and VESIMOS-DP was done to show the advantages of incorporating dielectric pocket (DP) to the performance of the device. An improved stability of threshold voltage, VTH was found for VESIMOS-DP device of various DP size ranging from 20nm to 80nm. The stability is due to the reducing charge sharing effects between source and drain region. However, the presence of DP layer has introduced another potential barrier in addition to the delta p+ (δp+) triangular potential barrier. Thus, increased amount of gate voltage needed to overcome those barriers and allows the electrons to flow from source to drain. Moreover, the DP layer has suppressed the parasitic bipolar transistor effect (PBT) with higher breakdown voltage as compared to without DP layer. Hence, the incorporation of DP into VESIMOS has enhanced its performance and presents elevated characteristics for nano-electronics device.

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Emerging Fet Architectures

Sahay¹,

Kumar²

2019

Junctionless Field‐Effect Transistors

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Investigation of the performance of strained-SiGe vertical IMOS-transistors

Cited by 17 publications

References 43 publications

Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Body doping analysis of vertical strained-SiGe Impact Ionization MOSFET incorporating dielectric pocket (VESIMOS-DP)

Performance Analysis of Vertical Strained-SiGe Impact Ionization MOSFET Incorporating Dielectric Pocket (VESIMOS-DP)

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