Vertex Detectors for a Super-B factory

Rizzo, G.

doi:10.22323/1.057.0040

Cited by 4 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus full CMOS circuitry is possible such that complete signal processing chains like charge sensitive preamplifier, discriminator, shaper plus logic can be realized within the pixel cell. The response of a prototype matrix (APSEL3 [35]) to a 90 Sr β-source is shown in fig. 11(b).…”

Section: Maps-epimentioning

confidence: 99%

“…The S/N = 23 is measured. Pixel matrices (32 × 128 pixels) with 50 µm pitch have been tested which collect the charge generated by an 55 Fe 6 keV X-ray source in one pixel [35]. Another approach uses a deep p-well [7] in a quadrupel well process called INMAPS to shield the n-wells containing PMOS transistors.…”

Section: Maps-epimentioning

confidence: 99%

“…(a) MAPS-epi development using a deep n-well structure (schematic layout[9]). (b) measured cluster signal (mV) with the APSEL3 prototype chip in response to a 90 Sr source[35]. The S/N is 23.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Pixel detectors for charged particles

Wermes

2009

Nuclear Instruments and Methods in Physics Research Section A:

View full text Add to dashboard Cite

a b s t r a c tPixel detectors, as the current technology of choice for the innermost vertex detection, have reached a stage at which large detectors have been built for the LHC experiments and a new era of developments, both for hybrid and for monolithic or semi-monolithic pixel detectors is in full swing. This is largely driven by the requirements of the upgrade programme for the superLHC and by other collider experiments which plan to use monolithic pixel detectors for the first time. A review on current pixel detector developments for particle tracking and vertexing is given, comprising hybrid pixel detectors for superLHC with its own challenges in radiation and rate, as well as on monolithic, so-called active pixel detectors, including monolithic active pixels (MAPS) and DEPFET pixels for RHIC and superBelle.

show abstract

Section: Maps-epimentioning

confidence: 99%

Section: Maps-epimentioning

confidence: 99%

See 1 more Smart Citation

Pixel detectors for charged particles

Wermes

2009

Nuclear Instruments and Methods in Physics Research Section A:

View full text Add to dashboard Cite

show abstract

“…The development of deep N-well (DNW) monolithic active pixel sensors (MAPS) was driven by the ambitious goal of implementing advanced readout functionalities (as in hybrid pixel detectors) in a monolithic device. In the first generation of DNW MAPS [1], designed in a 130 nm CMOS technology, data sparsification and time stamping are performed at pixel level, and different readout architectures are implemented taking into account the requirements of vertex detectors at the Super B-Factory [2] and the ILC [3]. In the pixel, the charge collecting electrode (the deep N-well) is extended over a relatively large fraction of the cell area.…”

Section: Introductionmentioning

confidence: 99%

Towards a high performance vertex detector based on 3D integration of deep N-well MAPS

2010

J. Inst.

View full text Add to dashboard Cite

The development of deep N-Well (DNW) CMOS active pixel sensors was driven by the ambitious goal of designing a monolithic device with similar functionalities as in hybrid pixel readout chips, such as pixel-level sparsification and time stamping. The implementation of the DNW MAPS concept in a 3D vertical integration process naturally leads the designer towards putting more intelligence in the chip and in the pixels themselves, achieving novel device structures based on the interconnection of two or more layers fabricated in the same technology. These devices are read out with a data-push scheme that makes it possible to use pixel data for the generation of a flexible level 1 track trigger, based on associative memories, with short latency and high efficiency. This paper gives an update of the present status of DNW MAPS design in both 2D and 3D versions, and presents a discussion of the architectures that are being devised for the Layer 0 of the SuperB Silicon Vertex Tracker.

show abstract

“…The R&D activity on Deep N-Well MAPS (DNW MAPS in the following) started about 5 years ago [1] with the aim of building monolithic sensors with similar functionalities as hybrid pixel systems, including data sparsification performed along with time stamping at the level of the single pixels. This requires to take full advantage of the potential of a subquartermicron CMOS technology, in order to integrate advanced analog and digital functions inside pixels with a small size (with a pitch of a few tens of a µm), as dictated by point resolution specifications of vertex detectors for the ILC [2] or the Super B-Factory [3]. On the other hand, a full CMOS design requires using PMOSFETs inside the pixels.…”

Section: Introductionmentioning

confidence: 99%

Status and perspectives of deep N-well 130 nm CMOS MAPS

2009

J. Inst.

View full text Add to dashboard Cite

Deep N-Well (DNW) MAPS were developed in two different flavors to approach the specifications of vertex detectors in dissimilar experimental environments such as the Super B-Factory and the ILC. The first generation of MAPS with on-pixel data sparsification and time stamping capabilities is now available and was tested in a beam for the first time in September 2008. These devices are fabricated in a commercial 130 nm CMOS process, and the triple well structure available in such an ultra-deep submicron technology is exploited by using the deep N-well as the charge-collecting electrode. Because of the high integration density of such a technology, complex digital functions can be included in each pixel, implementing a sparsified readout architecture of the pixel matrix with time stamping. This paper reviews the features of the "ILC class" and "SuperB class" MAPS devices, discussing their different design in terms of pixel pitch, analog signal processing, and digital readout architecture. For SuperB, a data-driven, continuously operating readout scheme was adopted along with a macropixel matrix arrangement, whereas for the ILC the matrix is read out in the long intertrain period. In both versions, the address of hit pixels is transmitted off-chip along with the time stamp. The experimental performance of the chips provides an assessment of the Deep N-Well MAPS potential in view of future applications. The paper also discusses the way forward in the development of these devices, outlining the issues that have to be tackled to design full size Deep N-Well MAPS for actual experiments. These sensors could take advantage from technological advances in microelectronic industry, such as vertical integration. The impact of these new technologies on the design and performance of DNW pixel sensors could be large, with potential benefit for various device features, from the charge collection properties to the digital readout architecture.

show abstract

Vertex Detectors for a Super-B factory

Cited by 4 publications

References 7 publications

Pixel detectors for charged particles

Pixel detectors for charged particles

Towards a high performance vertex detector based on 3D integration of deep N-well MAPS

Status and perspectives of deep N-well 130 nm CMOS MAPS

Contact Info

Product

Resources

About