Towards a high performance vertex detector based on 3D integration of deep N-well MAPS

Abstract

The development of deep N-Well (DNW) CMOS active pixel sensors was driven by the ambitious goal of designing a monolithic device with similar functionalities as in hybrid pixel readout chips, such as pixel-level sparsification and time stamping. The implementation of the DNW MAPS concept in a 3D vertical integration process naturally leads the designer towards putting more intelligence in the chip and in the pixels themselves, achieving novel device structures based on the interconnection of two or more layers fabricated in the same technology. These devices are read out with a data-push scheme that makes it possible to use pixel data for the generation of a flexible level 1 track trigger, based on associative memories, with short latency and high efficiency. This paper gives an update of the present status of DNW MAPS design in both 2D and 3D versions, and presents a discussion of the architectures that are being devised for the Layer 0 of the SuperB Silicon Vertex Tracker.

Super B Vertex and Vertical integration

“…This multiproject wafer run will be handled by the integrated circuits brokers CMP, MOSIS and CMC. The deadline for this run is scheduled a few months after the delivery of 3D chips from a previous run in the same technology [13], where VIPIX submitted 3D MAPS prototypes with various architectures and pitches [14,15]. The CMOS wafers with the two separate tiers of these CMOS sensors were delivered at the end of 2010.…”

3D vertical integration technologies for advanced semiconductor radiation sensors and readout electronics

“…In the digital tier, the pixel-level logic (not shown in Fig. 2) enables a sparsified, time-ordered triggered readout of the pixel matrix [6]. This feature is especially useful in applications of this device to vertex detectors in high energy physics experiments, where the so-called Level 1 Trigger signal is generated only when interesting physics events are detected.…”