VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis

Esmaeilzadeh, Hadi; Ghodrati, Soroush; Gu, Jie; Guo, Shiyu; Kahng, Andrew B.; Kim, Joon-Kyung; Kinzer, Sean; Mahapatra, Rohan; Manasi, Susmita Dey; Mascarenhas, Edwin; Sapatnekar, Sachin S.; Varadarajan, Ravi; Wang, Zhiang; Xu, Hanyang; Yatham, Brahmendra Reddy; Zeng, Ziqing

doi:10.1109/iccad51958.2021.9643449

Cited by 10 publications

(7 citation statements)

References 5 publications

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“…Approach (1) consists of solutions like VeriGOOD-ML [3], which maps ML models described in the ONNX format to three substantially different architecture templates for different types of neural networks through the PolyMath compiler. GEMMINI [5] provides a parametrized systolic array generator in Chisel that connects to a RISC-V core; the GEMMINI toolchain then offloads operations from specific layers of ONNX models to the systolic array.…”

Section: Related Workmentioning

confidence: 99%

Bridging Python to Silicon: The SODA Toolchain

et al. 2022

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Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. We present the SODA Synthesizer, a modular and open-source hardware compiler that provides automated endto-end synthesis from high-level software frameworks to ASIC implementation, relying on multi-level representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 GFLOPS/W efficiency (32-bit precision) on typical convolutional neural network operators.

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Section: Related Workmentioning

confidence: 99%

Bridging Python to Silicon: The SODA Toolchain

et al. 2022

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“…One common approach to reduce design efforts of processing elements at the register-transfer level is to compile and map a high-level description of the input algorithm onto parametrized hardware modules and architecture templates. VeriGOOD-ML [22] uses the PolyMath compiler [23] to map ML models in the ONNX format to three different architecture templates designed for different types of neural networks. GEMMINI [24] offloads operations from specific layers of ONNX models to a systolic array connected to a RISC-V core, after building the systolic array itself starting from a parametrized generator in Chisel.…”

Section: Hardware Acceleration For Machine Learningmentioning

confidence: 99%

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

Curzel

Agostini

Castellana

et al. 2022

IEEE Trans. Comput.

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Edge systems are required to autonomously make real-time decisions based on large quantities of input data under strict power, performance, area, and other constraints. Meeting these constraints is only possible by specializing systems through hardware accelerators purposefully built for machine learning and data analysis algorithms. However, data science evolves at a quick pace, and manual design of custom accelerators has high non-recurrent engineering costs: general solutions are needed to automatically and rapidly transition from the formulation of a new algorithm to the deployment of a dedicated hardware implementation. Our solution is the SOftware Defined Architectures (SODA) Synthesizer, an end-to-end, multi-level, modular, extensible compiler toolchain providing a direct path from machine learning tools to hardware. The SODA Synthesizer frontend is based on the multilevel intermediate representation (MLIR) framework; it ingests pre-trained machine learning models, identifies kernels suited for acceleration, performs high-level optimizations, and prepares them for hardware synthesis. In the backend, SODA leverages state-of-the-art high-level synthesis techniques to generate highly efficient accelerators, targeting both field programmable devices (FPGAs) and applicationspecific circuits (ASICs). In this paper, we describe how the SODA Synthesizer can also assemble the generated accelerators (based on the finite state machine with datapath model) in a custom system driven by a distributed controller, building a coarse-grained dataflow architecture that does not require a host processor to orchestrate parallel execution of multiple accelerators. We show the effectiveness of our approach by automatically generating ASIC accelerators for layers of popular deep neural networks (DNNs). Our high-level optimizations result in up to 74x speedup on isolated accelerators for individual DNN layers, and our dynamically scheduled architecture yields an additional 3x performance improvement when combining accelerators to handle streaming inputs.

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“…1 illustrates the general framework of SimDIT, our simulator for DNN inference and training for ASIC-based DNN accelerators. ASIC accelerator platforms comprise hardware components that execute operations within a DNN workload [1], [11], [15]. We classify these operations as: (1) Conv, in convolution and fully-connected (FC) layers.…”

Section: General Framework Of Simditmentioning

confidence: 99%

“…Our target hardware platform is a general ASIC-based systolic DNN accelerator, similar to TPUv2 [1] and GeneSys [11]. Fig.…”

Section: Asic Hardware Platformmentioning

confidence: 99%

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Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms

Esmaeilzadeh

Ghodrati

Kahng

et al. 2022

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD

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Today's performance analysis frameworks for deep learning accelerators suffer from two significant limitations. First, although modern convolutional neural network (CNNs) consist of many types of layers other than convolution, especially during training, these frameworks largely focus on convolution layers only. Second, these frameworks are generally targeted towards inference, and lack support for training operations. This work proposes a novel performance analysis framework, SimDIT, for general ASIC-based systolic hardware accelerator platforms. The modeling effort of SimDIT comprehensively covers convolution and non-convolution operations of both CNN inference and training on a highly parameterizable hardware substrate. SimDIT is integrated with a backend silicon implementation flow and provides detailed end-to-end performance statistics (i.e., data access cost, cycle counts, energy, and power) for executing CNN inference and training workloads. SimDIT-enabled performance analysis reveals that on a 64×64 processing array, non-convolution operations constitute 59.5% of total runtime for ResNet-50 training workload. In addition, by optimally distributing available off-chip DRAM bandwidth and on-chip SRAM resources, SimDIT achieves 18× performance improvement over a generic static resource allocation for ResNet-50 inference.

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VeriGOOD-ML: An Open-Source Flow for Automated ML Hardware Synthesis

Cited by 10 publications

References 5 publications

Bridging Python to Silicon: The SODA Toolchain

Bridging Python to Silicon: The SODA Toolchain

End-to-End Synthesis of Dynamically Controlled Machine Learning Accelerators

Physically Accurate Learning-based Performance Prediction of Hardware-accelerated ML Algorithms

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