Bridging Python to Silicon: The SODA Toolchain

Agostini, Nicolas Bohm; Curzel, Serena; Zhang, Jeff; Limaye, Ankur; Tan, Cheng; Amatya, Vinay; Minutoli, Marco; Castellana, Vito Giovanni; Manzano, Joseph; Brooks, David; Wei, Gu-Yeon; Tumeo, Antonino

doi:10.1109/mm.2022.3178580

Cited by 12 publications

(7 citation statements)

References 11 publications

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“…Furthermore, integrating solutions like LS Oracle [15] in the OpenROAD flow, which further optimizes the logic synthesis process, will allow another level of design space exploration across the tools, potentially without even directly exploiting resource characterization. Similarly, we have demonstrated [3] support for commercial logic synthesis tools (Synopsys Design Compiler) and leading-edge proprietary PDKs (Global Foundries 14/16 nm) previously. However, we cannot distribute the information obtained through the resource characterization step due to license agreements and the resource characterization must be repeated every time.…”

Section: Research Opportunitiesmentioning

confidence: 81%

“…In such a context, we introduce the SODA (Software Defined Accelerators) Synthesizer [3], an open-source, modular, and extensible end-to-end compiler-based framework for generating highly specialized hardware accelerators from algorithms designed in highlevel programming frameworks. SODA is composed of a compilerbased frontend to interface with high-level programming frameworks and apply high-level optimizations, and a compiler-based backend to generate Verilog code and interface with external tools that compile the final design (either application-specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs).…”

Section: Introductionmentioning

confidence: 99%

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SODA Synthesizer

Agostini

Limaye

Minutoli

et al. 2022

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

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The SODA Synthesizer is an open-source, modular, end-to-end hardware compiler framework. The SODA frontend, developed in MLIR, performs system-level design, code partitioning, and highlevel optimizations to prepare the specifications for the hardware synthesis. The backend is based on a state-of-the-art high-level synthesis tool and generates the final hardware design. The backend can interface with logic synthesis tools for field programmable gate arrays or with commercial and open-source logic synthesis tools for application-specific integrated circuits. We discuss the opportunities and challenges in integrating with commercial and open-source tools both at the frontend and backend, and highlight the role that an end-to-end compiler framework like SODA can play in an open-source hardware design ecosystem.

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Section: Research Opportunitiesmentioning

confidence: 81%

Section: Introductionmentioning

confidence: 99%

SODA Synthesizer

Agostini

Limaye

Minutoli

et al. 2022

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design

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“…Thus, they fail to efficiently (i.e., without incurring the aforementioned runtime costs) produce feasible and low-latency designs. One notable recent work is the SODA Synthesizer [8], which does not rely on a commercial tool but instead relies on the open-source PandA-Bambu HLS tool [18]; though open-source and mature, we found in our own tests that PandA-Bambu also could not handle fully unrolled designs efficiently.…”

Section: Related Workmentioning

confidence: 84%

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Levental¹,

Khan²,

Chard³

et al. 2023

Preprint

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In many experiment-driven scientific domains, such as high-energy physics, material science, and cosmology, high data rate experiments impose hard constraints on data acquisition systems: collected data must either be indiscriminately stored for post-processing and analysis, thereby necessitating large storage capacity, or accurately filtered in real-time, thereby necessitating low-latency processing. Deep neural networks, effective in other filtering tasks, have not been widely employed in such data acquisition systems, due to design and deployment difficulties. We present an open source, lightweight, compiler framework, without any proprietary dependencies, OpenHLS, based on high-level synthesis techniques, for translating high-level representations of deep neural networks to low-level representations, suitable for deployment to near-sensor devices such as field-programmable gate arrays. We evaluate OpenHLS on various workloads and present a case-study implementation of a deep neural network for Bragg peak detection in the context of high-energy diffraction microscopy. We show OpenHLS is able to produce an implementation of the network with a throughput 4.8 µs/sample, which is approximately a 4× improvement over the existing implementation.

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“…Although HLS methods such as C++ based [29], Python based [30] and Julia based [31] have been used in the literature, Simulink/HDL Coder has been used as the HLS tool in this study because it offers a visual-based development environment, well-organized guidelines and extra tools such as HDL Workflow Advisor and Fixed-Point Designer.…”

Section: Area-efficient Fpga Design Workflowmentioning

confidence: 99%

Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator

Memis,

Yeniceri

2024

IEEE Access

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The mathematical model of a 6-DoF dynamics is used in different applications. In general, to implement the 6-DoF dynamic model, software-based solutions are utilized. This paper introduces FPGAbased implementation of the 6-DoF dynamics accelerator. The proposed hardware-based approach ensures model accuracy in a nonlinear manner without compromising computational speed. In the design and implementation stages, the model-based approach and high-level synthesis have been employed. In terms of design strategy, standard processor architecture and resource sharing methods have been applied to achieve FPGA resource efficiency. In total, 7 datapath and a finite state machines have been designed for 7 different subsystems. The design resulted in hardware blocks that can execute all non-linear model equations 396 times in 1 ms using fixed/floating-point hybrid case, and 434 times using pure fixed-point case. The model equations, which took an average of 0.4986 s to simulate in the Simulink environment, have been run on an FPGA in 7.1924 µs. For 7 different design cases, numerical errors, resource utilization and timing metrics are tabulated and presented to the reader.INDEX TERMS 6-DoF, FPGA, Model-based design, High-level synthesis, Dynamics, Quadrotor.

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Bridging Python to Silicon: The SODA Toolchain

Cited by 12 publications

References 11 publications

SODA Synthesizer

SODA Synthesizer

OpenHLS: High-Level Synthesis for Low-Latency Deep Neural Networks for Experimental Science

Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator

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