Verifying VHDL designs with COSPAN

Fisler, Kathi; Kurshan, Robert P.

doi:10.1007/3-540-63475-4_5

Cited by 7 publications

(5 citation statements)

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“…In comparison with other techniques applied to the same case studies, e.g. COSPAN [8] and CIRCAL [20], DILL is much more convenient for giving a higher-level specification. This is not so surprising since LOTOS is an expressive language.…”

Section: Resultsmentioning

confidence: 99%

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Specification and Verification of Synchronous Hardware using LOTOS

Turner

1999

IFIP Advances in Information and Communication Technology

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Abstract:This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Ca:sar/Aldebaran Development Package).

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Section: Resultsmentioning

confidence: 99%

“…COSP AN can verify an arbiter with four cells with the consumption of about 1 MB memory, due to a symbolic representation using BDDs and efficient reduction techniques [8]. CIRCAL is reported to generate the state space of an arbiter with up to 40 cells using reasonable computing resources, although the actual memory used was not reported [20].…”

Section: Resultsmentioning

confidence: 99%

Specification and Verification of Synchronous Hardware using LOTOS

Turner

1999

IFIP Advances in Information and Communication Technology

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“…The proof system and the proof generation process draw on results which relate model checking for the μ-calculus to winning parity games [23]. The system was implemented (as a prototype) on top of a BDD-based engine (COSPAN [25]); it is however unclear how to adapt it to modern SAT-based engines. Our approach instead implements proof generation on top of SAT-based algorithms without any substantial overhead or modification of the model checking engine.…”

Section: Related Work and Contributionsmentioning

confidence: 99%

Certifying proofs for SAT-based model checking

Griggio

Roveri

Tonetta

2021

Form Methods Syst Des

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In the context of formal verification, certifying proofs are evidences of the correctness of a model in a deduction system produced automatically as outcome of the verification. They are quite appealing for high-assurance systems because they can be verified independently by proof checkers, which are usually simpler to certify than the proof-generating tools. Model checking is one of the most prominent approaches to formal verification of temporal properties and is based on an algorithmic search of the system state space. Although modern algorithms integrate deductive methods, the generation of proofs is typically restricted to invariant properties only. Moreover, it assumes that the verification produces an inductive invariant of the original system, while model checkers usually involve a variety of complex pre-processing simplifications. In this paper we show how, exploiting the k-liveness algorithm, to extend proof generation capabilities for invariant checking to cover full linear-time temporal logic (LTL) properties, in a simple and efficient manner, with essentially no overhead for the model checker. Besides the basic k-liveness algorithm, we integrate in the proof generation a variety of widely used pre-processing techniques such as temporal decomposition, model simplification via computation of equivalences with ternary simulation, and the use of stabilizing constraints. These techniques are essential in many cases to prove that a property holds, both for invariant and for LTL model checking, and thus need to be considered within the proof. We implemented the proof generation techniques on top of IC3 engines, and show the feasibility of the approach on a variety of benchmarks taken from the literature and from the Hardware Model Checking Competition. Our results confirm that proof generation results in negligible overhead for the model checker.

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“…We then refine the assertion graph in Figure 4 by applying the same refinements that refine the original assertion graph to the refined assertion graph and get the determinized and refined assertion graph shown in Figure 5. We select COSPAN [24,25] as the model checking engine to perform language containment test. We code the automata corresponding to the assertion graphs in Figures 4 and 5 in S/R, the input language of COSPAN, and use COSPAN to verify that the language of the automaton corresponding to the assertion graph in Figure 4 is contained in the language of the assertion graph in Figure 5.…”

Section: Casementioning

confidence: 99%

A Transformation-Based Approach to Implication of GSTE Assertion Graphs

Yang

Hung

Song

et al. 2013

Journal of Applied Mathematics

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Generalized symbolic trajectory evaluation (GSTE) is a model checking approach and has successfully demonstrated its powerful capacity in formal verification of VLSI systems. GSTE is an extension of symbolic trajectory evaluation (STE) to the model checking ofω-regular properties. It is an alternative to classical model checking algorithms where properties are specified as finite-state automata. In GSTE, properties are specified as assertion graphs, which are labeled directed graphs where each edge is labeled with two labeling functions: antecedent and consequent. In this paper, we show the complement relation between GSTE assertion graphs and finite-state automata with the expressiveness of regular languages andω-regular languages. We present an algorithm that transforms a GSTE assertion graph to a finite-state automaton and vice versa. By applying this algorithm, we transform the problem of GSTE assertion graphs implication to the problem of automata language containment. We demonstrate our approach with its application to verification of an FIFO circuit.

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Verifying VHDL designs with COSPAN

Cited by 7 publications

References 0 publications

Specification and Verification of Synchronous Hardware using LOTOS

Specification and Verification of Synchronous Hardware using LOTOS

Certifying proofs for SAT-based model checking

A Transformation-Based Approach to Implication of GSTE Assertion Graphs

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