Verifying SystemC using stateful symbolic simulation

Abstract

Formal verification of high-level SystemC designs is an important and challenging problem. Recent works have proposed symbolic simulation in combination with Partial Order Reduction (POR) as a promising solution and experimentally demonstrated its potential. However, these symbolic simulation approaches have a fundamental limitation in handling cyclic state spaces. The reason is that they are based on stateless model checking and thus unable to avoid revisiting states in a cycle. In this paper, we propose a novel stateful symbolic simulation approach for SystemC. For the efficient detection of revisited symbolic states, we apply symbolic subsumption checking. Furthermore, our implementation integrates a cycle proviso to preserve the soundness of POR in the presence of cycles. We demonstrate the scalability and the efficiency of the proposed approach using an extensive set of experiments.

Verifying next generation electronic systems

“…Cyclic state space support for symbolic simulation, which allows to prove safety properties, has been provided in [21]. This stateful symbolic simulation approach for SystemC applies symbolic subsumption checking for efficient detection of revisited symbolic states.…”

“…Further reading: [32], [14], [33], [12], [21], [34], [13], [19], [20], [35] Coverage metrics: Strong coverage metrics for formal verification at the Register Transfer Level (RTL) have been proposed. However, coverage at higher levels of abstraction is still very challenging.…”

Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution

“…Verification and testing SystemC designs (and, in general high level designs) for bug detection have a rich literature [10,[20][21][22][23][24]36]. Prior works adopt two mainstream approaches to tackle the problem: 1) formal techniques, and 2) simulationbased techniques.…”