Verification

Abstract

PANEL SUMMARYToday's leading chip and system companies are faced with ever increasing design verification challenges; industry studies reveal that as much as 50% of the total schedule is being spent in verification. Large companies, with almost infinite resources, have shown that throwing CPU cycles and people at the simulation problem still doesn't guarantee a level of coverage desired by the design team.So, what is the answer? Are assertions, faster simulators, and testbench languages the "holy grail", or are those just microoptimizations of a methodology that is fundamentally flawed? Is there hope for a verification methodology that completely covers a design with a predictable verification schedule?The panelists will describe their experiences of what works and what doesn't, providing insights into their methodologies and philosophies.