2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems 2008
DOI: 10.1109/ddecs.2008.4538784
|View full text |Cite
|
Sign up to set email alerts
|

Efficient Allocation of Verification Resources using Revision History Information

Abstract: Verifying large industrial designs is getting harder undetected bugs? In which modules the verification team each day. The current verification methodologies are not able to should concentrate their effort? The objective of this paper is to guarantee bug free designs. Some recurrent questions during use software engineering techniques to answer these questions. a design verification are: Which modules are most likely to contain undetected bugs? In which modules the verification The novelty of this work Si to p… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2009
2009
2011
2011

Publication Types

Select...
3

Relationship

1
2

Authors

Journals

citations
Cited by 3 publications
(1 citation statement)
references
References 19 publications
(9 reference statements)
0
1
0
Order By: Relevance
“…A modern approach is to identify error-prone modules to focus the available resources. Nacif et al [2] discuss methodologies to retrieve important information from concurrent versioning systems. The retrieved information was successfully used to predict which modules had more bugs.…”
Section: Introductionmentioning
confidence: 99%
“…A modern approach is to identify error-prone modules to focus the available resources. Nacif et al [2] discuss methodologies to retrieve important information from concurrent versioning systems. The retrieved information was successfully used to predict which modules had more bugs.…”
Section: Introductionmentioning
confidence: 99%