Verification of Complex Analog and RF IC Designs

Abstract

Meeting performance specifications in the design of Analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional A/RF design methodologies. Functionally verifying A/RF designs is a daunting task requiring a rigorous methodology. As occurred in digital design, analog verification is becoming a separate and critical task. This paper describes the verification issues faced by the A/RF designer and presents a verification methodology to address these challenges. It presents a systematic approach to A/RF verification, the concept of an analog verification engineer, how to establish the methodology, and concludes with an example.

Performance of a high-speed transcutaneous link with error correction coding

“…Also, another disadvantage of designs at this level is that they are not supported by transistor level simulators, preventing their cosimulation with transistor level designs [9]. Co-simulations of transistor level designs with higher design levels are desired, because they allow the designer to implement only the critical design areas at the transistor level, while representing the non-critical design areas at higher design levels, speeding up MS-RF-IC verifications.…”

“…Transistor level simulations also have been used to verify analog portions of wireless transceivers. However, due to the complexity (e.g., thousands of modes of operations and settings) of modern MS-ICs, transistor level simulations of a single IC mode can sometimes take a week or more, which may result highly impractical [9].…”

“…An MS system verification methodology was proposed by Chang and Kundert [9], in order to reduce the time to reach an MS-IC design that meets target specifications, and to reduce the risk of MS-IC functional failures. This methodology suggests the use of hardware description languages (HDL) and a mixed-signal simulator, for the RTL design and functional verification of MS systems.…”

“…An advantage of being able to verify an HDLbased RTL design of an MS system is that functional errors can be detected early in the IC development process, which can save money and time. These savings can occur since functional error corrections may be more difficult and time consuming at the transistor level design [9], and IC re-spins can be quite expensive nowadays [8]. Also, another advantage of RTL designs is that they can ease the re-use of MS-IC designs.…”

Formal approaches to analog circuit verification

“…This requires solving problems like unacceptable simulation time and the need for tremendous computation power, especially for the verification of RF front-ends with very high carrier frequencies [2], [3]. Therefore, the modeling of the subsystems and circuits becomes an indispensable task for the functional verification flow [4]. Hardware description languages offer the possibility to model the behavior of the circuits, reducing the number of equations by substituting the abstract coherences between the components with simpler mathematical descriptions of the circuits' behavior.…”