Formal approaches to analog circuit verification

Barke, Erich; Grabowski, Darius; Graeb, Helmut; Hedrich, Lars; Heinen, Stefan; Popp, R.; Steinhorst, Sebastian; Wang, Yifan

doi:10.1109/date.2009.5090759

Cited by 10 publications

(3 citation statements)

References 13 publications

(11 reference statements)

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“…Recent research on analog circuit verification can be distinguished into two categories: simulation-based methods and formal verification methods [1].…”

Section: Related Workmentioning

confidence: 99%

Causal reasoning mining approach to analog circuit verification

Jiao

Doboli

2016

Integration

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Functional errors in analog portion of mixed signal circuits become more severe and improvements in verification methods are increasingly important. Current verification methods fall into two categories, simulation-based verification and formal verification [1], focusing on verifying analog circuit function/performance. This paper proposes a novel approach verifying analog circuit design using causal reasoning. Causal reasoning is the inductive reasoning process to create a new design. The flow begins with mining the causal reasoning steps (design plan) that produced the circuit, including starting ideas, design step sequence, and their justifications [2]. Then, topological features corresponding to the starting ideas and design step sequence are verified individually by replacing the related devices with ideal behavior model. Performance is evaluated through Cadence Spectre simulation. Comparison with new circuit performance reveals incorrect functional issues and/or performance potentials for improvement. They are negative causes of certain starting ideas or design steps, which might have been omitted during the design process. The paper discusses three operational amplifier designs realized in 0.2-µm CMOS technology to illustrate the verification approach.

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“…Recent research on analog circuit verification can be distinguished into two categories: simulation-based methods and formal verification methods [1].…”

Section: Related Workmentioning

confidence: 99%

Causal reasoning mining approach to analog circuit verification

Jiao

Doboli

2016

Integration

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“…Formal approaches like [11], [12], [13], [14], [15], [16] and semiformal approaches like [1], [2], [3], [17] are two main branches in the field. Mathematical origins of these approaches have Maler and Nickovic [18], [19] presented Signal Temporal Logic, STL, to monitor temporal properties of continuous signals by extending Metric Interval Time Logic, MITL [10].…”

Section: Related Workmentioning

confidence: 99%

Using haloes in mixed-signal assertion based verification

Ulus

Şen

2012

2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

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Abstract-We develop an assertion based verification solution for analog mixed-signal designs. We introduce the halo concept for analog signals to express them with their tolerance and variation values in assertions. The halo of a signal provides a relaxation over the signal and it defines an effective region for that signal which can be used in assertion based verification. Using haloes for analog signals allow us to define a new set of comparison relations between two analog signals including their equivalence. In our intended design flow, these new analog signal operators are placed into the Analog layer of mixed-signal assertion languages as an extension. We present experimental results on a programmable switch and a VCO.

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“…Moreover, it is well known that for large circuits model checking can easily run into statespace explosion. By contrast, formal methods in particular, theorem proving can deliver the highest level of assurance for verification [5]. Akbarpour and Paulson [2] have very recently proposed an automatic proof procedure for inequalities on elementary functions, called MetiTarski, which we will adopt in this paper.…”

Section: Introductionmentioning

confidence: 99%

Formal verification of analog circuits in the presence of noise and process variation

Narayanan¹,

Akbarpour²,

Zaki³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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Abstract-We model and verify analog designs in the presence of noise and process variation using an automated theorem prover, MetiTarski. Due to the statistical nature of noise, we propose to use stochastic differential equations (SDE) to model the designs. We find a closed form solution for the SDEs, then integrate the device variation due to the 0.18µm fabrication process and verify properties using MetiTarski. We illustrate the proposed approach on an inverting Op-Amp Integrator and a Band-Gap reference bias circuit.

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Formal approaches to analog circuit verification

Cited by 10 publications

References 13 publications

Causal reasoning mining approach to analog circuit verification

Causal reasoning mining approach to analog circuit verification

Using haloes in mixed-signal assertion based verification

Formal verification of analog circuits in the presence of noise and process variation

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