Verification of asynchronous interface circuits with bounded wire delays

Abstract

We address the problem of verifying that the gatelevel implementation of an asynchronous circuit, with given or extracted bounds on wire and gate delays, is equivalent to a specification of the asynchronous circuit behavior described as a classical flow table, under the fundamental mode of operation.ive a procedure to extract the complete set of p o s s h e flow tables from a gate-level description of an asynchronous circuit under the bounded wire delay model. Given an extracted flow table and the initial flow table specification, we give procedures to construct a product flow table so as to check for machine equivalence.