Asynchronous Circuit Design: Motivation, Background, &amp; Methods

Davis, Al; Nowick, Steven M.

doi:10.1007/978-1-4471-3575-3_1

Cited by 36 publications

(14 citation statements)

References 64 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The latency insensitive design methodology is clearly reminiscent of many ideas which have been proposed in the asynchronous design community during the past three decades [11]. In particular, the idea of a design methodology which is inherently modular is already present in the work on Macromodular Computer Systems by Clark and Molnar [5,6].…”

Section: Latency Insensitive Vs Asynchronous Designmentioning

confidence: 99%

A Methodology for Correct-by-Construction Latency Insensitive Design

et al. 2003

View full text Add to dashboard Cite

show abstract

Section: Latency Insensitive Vs Asynchronous Designmentioning

confidence: 99%

A Methodology for Correct-by-Construction Latency Insensitive Design

et al. 2003

View full text Add to dashboard Cite

show abstract

“…Hence, previous relations (6)- (9) hold also in this case. Now, keeping in mind that here , it is easy to prove that: a) using (8) and (6), satisfy (4), ; b) using (9) and (6), satisfy (4), ; c) using (9) and (7), satisfy (4), ; d) using (6) and (8), satisfy (5), ; e) using 15 (6) and (8), satisfy (5), ; f) using (7) and (9) is patient. Consider a strict system with strict signals .…”

Section: Definition Iv2mentioning

confidence: 86%

“…The theory of latency-insensitive design is clearly reminiscent of many ideas which have been proposed in the asynchronous design community during the past three decades [15], [16]. In particular, the idea of a design methodology which is inherently modular is already present in the work by Clark and Molnar [17], [18].…”

Section: Background and Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Theory of latency-insensitive design

Carloni

McMillan

Sangiovanni-Vincentelli

2001

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

343

245

View full text Add to dashboard Cite

Abstract-The theory of latency-insensitive design is presented as the foundation of a new correct-by-construction methodology to design complex systems by assembling intellectual property components. Latency-insensitive designs are synchronous distributed systems and are realized by composing functional modules that exchange data on communication channels according to an appropriate protocol. The protocol works on the assumption that the modules are stallable, a weak condition to ask them to obey. The goal of the protocol is to guarantee that latency-insensitive designs composed of functionally correct modules behave correctly independently of the channel latencies. This allows us to increase the robustness of a design implementation because any delay variations of a channel can be "recovered" by changing the channel latency while the overall system functionality remains unaffected. As a consequence, an important application of the proposed theory is represented by the latency-insensitive methodology to design large digital integrated circuits by using deep submicrometer technologies.Index Terms-Deep submicrometer design, formal methods, latency-insensitive protocols, system design.

show abstract

“…They have no clock skew problem, can be designed for average-case rather than worst-case performance, have potentially lower power consumption, and have a higher degree of modularity [4]. However, as we mentioned above, several aspects of asynchronous circuits make them harder to test than synchronous circuits.…”

Section: Introductionmentioning

confidence: 97%

DUDES: a fault abstraction and collapsing framework for asynchronous circuits

Shirvani

Mitra

Ebergen

et al.

Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00

View full text Add to dashboard Cite

This paper addresses the problem of fault collapsing in asynchronous circuits. We investigate different transistor-level implementations of some basic elements that are used in delay-insensitive asynchronous circuit designs, and analyze them in the presence of single stuckat faults. From this analysis, we conclude that all internal stuck-at faults which are detectable by Boolean testing, can be represented as pin-faults. This abstraction makes it possible to perform fault simulation at the logic level (network of basic elements) rather than at transistor level, which reduces the simulation time. We show how this fault model, called DUDES, can be used for fault collapsing to reduce the size of fault lists at the logic level, thereby reducing the simulation time even further. We set the basis for a formal technique for deriving equivalence relationships among the faults under consideration, using trace expressions, and illustrate that this formal technique also supports fault collapsing at the system level. This framework can be expanded to a theory of fault abstraction and collapsing for asynchronous circuits that can reduce the complexity of test pattern generation and fault simulation.

show abstract

Asynchronous Circuit Design: Motivation, Background, & Methods

Cited by 36 publications

References 64 publications

A Methodology for Correct-by-Construction Latency Insensitive Design

A Methodology for Correct-by-Construction Latency Insensitive Design

Theory of latency-insensitive design

DUDES: a fault abstraction and collapsing framework for asynchronous circuits

Contact Info

Product

Resources

About