Verification of all circuits in a floating-point unit using word-level model checking

Chen, Yirng-An; Clarke, Edmund M.; Ho, Pei-Hsin; Hoskote, Yatin; Kam, Timothy; Khaira, Manpreet; O’Leary, John; Zhao, Xudong

doi:10.1007/bfb0031797

Cited by 34 publications

(26 citation statements)

References 17 publications

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“…Jones et al 102,103 combined STE with theorem proving to formally verify an instruction decoder and a floating-point adder/subtracter from Intel processors. Chen et al 104 used word-level model checking to formally verify an Intel floatingpoint unit that could add, subtract, multiply, divide, round, and compute square root. Chen and Bryant 105 proved the correctness of floating-point adders and multipliers.…”

Section: Related Workmentioning

confidence: 99%

Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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Abstract. The paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors. The projects were integrated-by means of lectures and preparatory homework exercises-into an existing advanced computer architecture course taught to both undergraduate and graduate students in a way that required them to have no prior knowledge of formal methods. The first project was on design and formal verification of a 5-stage pipelined DLX processor, implementing the six basic instruction types-register-register-ALU, registerimmediate-ALU, store, load, jump, and branch. The second project was on extending the processor from project one with ALU exceptions, a return-from-exception instruction, and branch prediction; each of the resulting models was formally verified. The third project was on design and formal verification of a dual-issue superscalar version of the DLX from project one. The preparatory homework problems included an exercise on design and formal verification of a staggered ALU, pipelined in the style of the integer ALUs in the Intel Pentium 4. The processors were described in the high-level hardware description language AbsHDL that allows the students to ignore the bit widths of word-level values and the internal implementations of functional units and memories, while focusing entirely on the logic that controls the pipelined or superscalar execution. The formal verification tool flow included the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker; this tool flow-combined with the same abstraction techniques for defining processors with exceptions and branch prediction, as used in the projects-was applied at Motorola to formally verify a model of the M•CORE processor, and detected bugs. The course went through two iterations-offered at the Georgia Institute of Technology in the summer and fall of 2002-and was taught to 67 students, 25 of whom were undergraduates.

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Section: Related Workmentioning

confidence: 99%

Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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“…Nevertheless, only fully complete specifications should be used to validate implementations. The flag error of the integer conversion first detected by a user with a Pentium Pro [7] had not been detected earlier because specifications used at Intel were not complete [5,27].…”

Section: Fallacies and Pitfallsmentioning

confidence: 99%

Properties of two’s complement floating point notations

Boldo

Daumas

2004

STTT

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Abstract. Few designs, mostly those of Texas Instruments, continue to use two's complement floating point units. Such units are simpler to build and to validate, but they do not comply to the dominant IEEE standard for floating point arithmetic. We compare some properties of the two systems in this text. Some features are lost, but others remain unchanged. One strong example is the case of Sterbenz's theorem and our recent extension. We show in the paper that the theorem and its extension hold for the two's complement architecture. Still, users should ensure that results are large enough on circuits that do not implement gradual underflow. Theorems have been proven and validated using the Coq automatic proof checker.

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“…The correctness of an important collection of floating point algorithms is shown in [21,22] using the theorem prover ACL2. Correctness proofs using a combination of theorem proving and model checking techniques for the FPUs of Pentium processors are claimed in [4,19]. As the verified unit is part of an industrial product not all details have been published.…”

Section: Introductionmentioning

confidence: 99%

Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP

Beyer

Jacobi²,

Kröning

et al. 2003

Lecture Notes in Computer Science

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Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA.

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Verification of all circuits in a floating-point unit using word-level model checking

Cited by 34 publications

References 17 publications

Integrating Formal Verification into an Advanced Computer Architecture Course

Integrating Formal Verification into an Advanced Computer Architecture Course

Properties of two’s complement floating point notations

Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP

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