Vectorized Big Integer Operations for Cryptosystems on the Intel MIC Architecture

Chang, Cheng; Yao, Shun; Yu, D.

doi:10.1109/hipc.2015.54

Cited by 9 publications

(4 citation statements)

References 16 publications

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“…Implementations targeting hardware on which efficient carry propagation mechanisms exist tend to use full-radix representations. Examples include general-purpose CPUs [9,14] and GPUs [5,6], and the first generation Xeon Phi codenamed Knight's Corner (KNC) [3,15,30]. However, the parallelization strategies differ.…”

Section: Related Workmentioning

confidence: 99%

Parallel modular multiplication using 512-bit advanced vector instructions

2021

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Applications such as public-key cryptography are critically reliant on the speed of modular multiplication for their performance. This paper introduces a new block-based variant of Montgomery multiplication, the Block Product Scanning (BPS) method, which is particularly efficient using new 512-bit advanced vector instructions (AVX-512) on modern Intel processor families. Our parallel-multiplication approach also allows for squaring and sub-quadratic Karatsuba enhancements. We demonstrate $$1.9\,\times $$ 1.9 × improvement in decryption throughput in comparison with OpenSSL and $$1.5\,\times $$ 1.5 × improvement in modular exponentiation throughput compared to GMP-6.1.2 on an Intel Xeon CPU. In addition, we show $$1.4\,\times $$ 1.4 × improvement in decryption throughput in comparison with state-of-the-art vector implementations on many-core Knights Landing Xeon Phi hardware. Finally, we show how interleaving Chinese remainder theorem-based RSA calculations within our parallel BPS technique halves decryption latency while providing protection against fault-injection attacks.

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Section: Related Workmentioning

confidence: 99%

Parallel modular multiplication using 512-bit advanced vector instructions

2021

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“…Let p and q be two primes such that p = 2q + 1. Since the computational cost of some cryptographic operations such as modular multiplication, hash function or inverse is relatively small after being optimized by various technologies [34], we consider only the computationally expensive bilinear pairing and exponentiation operations in Table 1. We use the symbol P to denote one paring operation.…”

Section: Comparisonmentioning

confidence: 99%

Strong Designated Verifier Signature Scheme with Undeniability and Strong Unforgeability in the Standard Model

Yang

Chen

et al. 2019

Applied Sciences

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Strong designated verifier signature can provide an efficient way to protect the identity privacy of the signer and the integrity of the data transmitted over the public channel. These characteristics make it very useful in outsourcing computing, electronic voting, electronic bidding, electronic auction and other fields. However, most strong designated verifier signature schemes are unable to identify the real signature generator when the signer and the designated verifier dispute a signature. In addition, the existing strong designated verifier signature schemes in the standard model rarely satisfy strong unforgeability, and thus cannot prevent the attacker from forging a valid signature on any previously signed message. Therefore, designing a strong designated verifier signature scheme without random oracles that satisfies strong unforgeability and undeniability is very attractive in both practice and theory. Motivated by these concerns, we design the first undeniable strong designated verifier signature scheme without random oracles, in which the arbiter can independently perform the judgment procedure to prove whether a controversial signature is generated by the signer or the designated verifier. Under standard assumptions, the scheme is proved to be strongly unforgeable in standard model. Furthermore, it not only achieves non-transferability and privacy of the signer’s identity but also satisfies the undeniable property of traditional digital signature schemes. Performance analysis results show that the length of the signer’s private key, the designated verifier’s private key and signature length are 40 bits, 40 bits and 384 bits, respectively. Compared with he related schemes, the proposed scheme has higher performance in signature length, private key size and computational overhead. Finally, we show how to apply it to implement outsourcing computation in cloud computing.

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“…The use of vector instructions for cryptographic algorithm optimization, however, is quite common. Chang et al presented an optimized implementation of the RSA algorithm, which achieved speedups of 4.3 to 5.9 times using the AVX‐512 instruction set, and Hamburg presented an implementation of elliptic‐curve cryptography using SSE and AVX instructions. Considering the code‐based cryptography field, specifically, there are also some optimization works using vector instructions.…”

Section: Related Workmentioning

confidence: 99%

Optimized implementation of QC‐MDPC code‐based cryptography

Guimarães

Aranha

Borin

2018

Concurrency and Computation

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Summary This paper presents a new enhanced version of the QcBits key encapsulation mechanism, which is a constant‐time implementation of the Niederreiter cryptosystem using QC‐MDPC codes. In this version, we updated the implementation parameters to meet the 128‐bit quantum security level, replaced some of the core algorithms to avoid using slower instructions, vectorized the entire code using the AVX‐512 instruction set extension, and applied several other techniques to achieve a competitive performance level. Our implementation takes 928, 259, and 5008 thousand Skylake cycles to perform batch key generation (cost per key), encryption, and uniform decryption, respectively. Comparing with the current state‐of‐the‐art implementation for QC‐MDPC codes, BIKE, our code is 1.9 times faster when decrypting messages.

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Vectorized Big Integer Operations for Cryptosystems on the Intel MIC Architecture

Cited by 9 publications

References 16 publications

Parallel modular multiplication using 512-bit advanced vector instructions

Parallel modular multiplication using 512-bit advanced vector instructions

Strong Designated Verifier Signature Scheme with Undeniability and Strong Unforgeability in the Standard Model

Optimized implementation of QC‐MDPC code‐based cryptography

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