Variation tolerant logic mapping for crossbar array nano architectures

Tunc, Cihan; Tahoori,

doi:10.1109/aspdac.2010.5419682

Cited by 12 publications

(21 citation statements)

References 17 publications

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“…Since variation optimization using exhaustive methods is an NP-Complete problem, we propose a heuristic algorithm for efficient runtime and optimization and compare it with a Simulated Annealing framework. This work complements our previous work which addressed offline variation tolerant mapping for FET-based crossbars, with different delay models and cost functions compared to diode-based crossbars, using simulated annealing [24].…”

Section: Introductionmentioning

confidence: 57%

Variation and defect tolerance for diode-based nano crossbars

Tahoori

2010

Nano Communication Networks

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Section: Introductionmentioning

confidence: 57%

Variation and defect tolerance for diode-based nano crossbars

Tahoori

2010

Nano Communication Networks

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“…One feature we are considering including in the defect-unaware design flow is variation of the characteristics of the devices in the crossbar architectures, which has been recently introduced in defect-aware design flow [Tunc and Tahoori 2010;Ghavami et al 2010]. There are various sources of variations in the characteristics of nanoelectronic devices, for example, the low controllability of manufacturing process results in variations in nanowire geometries.…”

Section: Disscussions and Future Workmentioning

confidence: 99%

A Fast Extraction Algorithm for Defect-Free Subcrossbar in Nanoelectronic Crossbar

Yuan

2014

J. Emerg. Technol. Comput. Syst.

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Due to the super scale, high defect density, and per-chip designing paradigm of emerging nanoelectronics, the runtime of the algorithms for defect-tolerant design is of vital importance from the perspective of practicability. In this article, an efficient and effective heuristic defect-free subcrossbar extraction algorithm is proposed which improves performance by mixing the heuristics from two state-of-the-art algorithms and then is speeded up significantly by considerably reducing the number of major loops. Compared with the current most effective algorithm that improves the solution quality (i.e., size of the defect-free subcrossbar obtained) at the cost of high time complexity O(n 3 ), the time complexity of the proposed heuristic algorithm is proved to be O(n 2 ). Using a large set of instances of various scales and defect densities, the simulation results show that the proposed algorithm can offer similar high-quality solutions as the current most effective algorithm while consuming much shorter runtimes (reduced to about 1/3 to 1/5) than the current most effective algorithm. ACM Reference Format:Bo Yuan and Bin Li. 2014. A fast extraction algorithm for defect-free subcrossbar in nanoelectronic crossbar.

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“…This will have a drastic effect on the overall yield under high defect density. A simulated annealing (SA) algorithm is used for variation tolerant mapping on a crossbar [30]. One disadvantage of this method is that it does not fit for multi-output two-level nanoscale crossbars, such as AND-OR logics.…”

Section: Previous Workmentioning

confidence: 99%

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

Ghavami

2016

J Comput Electron

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Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation-and defectaware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement.

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Variation tolerant logic mapping for crossbar array nano architectures

Cited by 12 publications

References 17 publications

Variation and defect tolerance for diode-based nano crossbars

Variation and defect tolerance for diode-based nano crossbars

A Fast Extraction Algorithm for Defect-Free Subcrossbar in Nanoelectronic Crossbar

Joint defect- and variation-aware logic mapping of multi-outputs crossbar-based nanoarchitectures

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