Variation tolerant buffered clock network synthesis with cross links

Abstract

Clock network synthesis is a key step in the ultra deep submicron (UDSM) VLSI Designs. Most existing clock network synthesis algorithms are designed for nominal operating condition, which are insufficient to address the growing problem of process, voltage and temperature (PVT) fluctuations. Link based clock networks have been suggested as a possible way of reducing skew variability [1-3]. However, [1,2] deal with only unbuffered clock networks, making them impractical. In [3], the problem of constructing a link based buffered clock network has been addressed . But [3] requires special kind of tunable buffers, which might consume more area/power and might not be available for all designs. Also, [3] uses SPICE for tuning the locations of internal nodes and buffer delays, thereby making it slow even for clock networks with a few hundred sinks. In this paper, we propose a unified algorithm for synthesizing a variation tolerant, balanced buffered clock network with cross links. Our approach can make use of ordinary buffers and does not require SPICE for clock network synthesis. SPICE based Monte Carlo simulations show that our methodology results in a buffered clock network with 50% reduction in skew variability with minimal increase in wire-length, buffer area and CPU time.

Multilevel tree fusion for robust clock networks

“…These methods are later extended to handle buffered clock trees in [17], [25]. While most crosslink insertion techniques do not seem competitive with best tree-tuning approaches, a recent cross-link scheme proposed in [13] achieves low overall capacitance by inserting cross links between internal nodes of a clock tree to reduce the total crosslink length.…”

Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond

“…The non-tree clock network can be either obtained by starting from a tree and gradually adding cross links between the sinks [53], [55] or by starting off with a complete mesh and removing parts of the mesh to reduce wirelength [61]. These techniques essentially take advantage of the robustness from clock mesh while lowing the wirelength/power overhead.…”

Power efficient tree-based crosslinks for skew reduction

“…maintain balance. Non-tree topologies vary from a tree with a limited number of additional crosslinks [9]- [12] to a complete mesh structure [5]- [8], where a crosslink is a wire segment that connects two tree nodes and a mesh is a set of crosslinks that connects all or a significant group of adjacent nodes within a specific level of a clock tree (see Figure 1). Mesh structures are designed to balance each of the clock delays at the leaves or at some intermediate level of the tree [5]- [8].…”

“…In the case of misaligned inputs, an additional issue should be considered: short-circuit current may flow through the crosslink and the two buffers, as illustrated in Figure 2 by the dotted line, dissipating additional power. Crosslink insertion has been proposed for reducing skew variations only between those pairs of nodes that target zero nominal skew [9]- [12]. However, power aspects have not been presented in these works; notably, inserting crosslinks, which may introduce short-circuit current, has not been discussed [10].…”

“…Despite the possibility of increasing the skew variation by inserting a crosslink, the authors in [12] propose an effective algorithm that significantly reduces the skew variation. Additional research [9], [10] has extended the algorithm in [12] to buffered clock trees, also exhibiting a reduction in skew variation. The rest of the paper is organized as follows.…”