Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

Guo, Yufeng; Yao, Jiafei; Zhang, Bo; Lin, Hong; Zhang, Changchun

doi:10.1109/led.2015.2393913

Cited by 68 publications

(36 citation statements)

References 14 publications

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“…Both the VLD and VLT are featured as their ability to achieve an even surface electric field profile and the most desirable lateral BV characteristic [10]- [12]. Due to the linear doping profile of VLD, a lightly doped drift region near the PN junction is formed which inevitably causes severe local self-heating and on-state characteristic deterioration [7], [9]. Moreover, the fabrication of VLD devices requires perforated mask layout and long-time/high-temperature annealing which increases costs and reduces yields [7], [9].…”

Section: Introductionmentioning

confidence: 99%

“…Due to the linear doping profile of VLD, a lightly doped drift region near the PN junction is formed which inevitably causes severe local self-heating and on-state characteristic deterioration [7], [9]. Moreover, the fabrication of VLD devices requires perforated mask layout and long-time/high-temperature annealing which increases costs and reduces yields [7], [9]. To avoid those drawbacks of VLD, VLT technique has been introduced which alter the drift region lateral charge distribution via variation of its thickness rather than doping.…”

Section: Introductionmentioning

confidence: 99%

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Effective Concentration Profile: A Novel 1-D Analysis of the Variation of Lateral Thickness (VLT) Lateral Power Devices

Zhang

Guo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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The VLT technique features for its irregular thickness of drift region and therefore realize the even surface electric field even with a uniformly doped drift region. However, the sophisticated structure of the drift region also making 2-D methods impractical in both modeling and explaining VLT's physical nature. In this paper, based on the Effective Concentration Profile (ECP) theory, a simple but effective 1-D modeling methodology is proposed to provide physical insight into the VLT technique. The VLT-ECP concept indicates that by physically removing the region that above Charge Appointment Line (CAL), the charge contributes to the lateral depletion can be reduced to zero leading to an even surface electric field. Further, an optimization criterion is proposed to provide useful guidance for the designing of VLT lateral power devices in practice. The comparison between the analytical results obtained by the proposed model and TCAD simulations verified the veracity and effectiveness of the proposed methodology. INDEX TERMS Variation of lateral thickness, 1-D model, effective concentration profile, breakdown voltage, lateral power device.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Effective Concentration Profile: A Novel 1-D Analysis of the Variation of Lateral Thickness (VLT) Lateral Power Devices

Zhang

Guo

Huang

et al. 2020

IEEE J. Electron Devices Soc.

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“…With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (R on,sp ) and maximizing off-state breakdown voltage (BV) [1][2][3][4][5][6][7][8][9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of R on,sp vs. BV for LDMOS devices [10][11][12][13][14][15][16][17][18][19][20]. In our previous work, the LDMOS with ultrashallow trench isolation (USTI) was proposed [21].…”

Section: Introductionmentioning

confidence: 99%

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

et al. 2019

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An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.

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“…[6] In our previous study, the Variation of Lateral Thickness (VLT) technique is proposed to uniformize the lateral electric field and maximize the lateral BV. [7] The Variation of Lateral Width technique together with the high-k dielectric (VLWHK) is also employed to improve the issue [8] . But complex fabricate process is required for the VLD, VLT, and VLW techniques.…”

Section: Introductionmentioning

confidence: 99%

Novel high-voltage LDMOS with linear graded drift region width

Yao

Guo

Zhang

et al. 2015

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)

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In this paper, a novel Lateral Diffused Metal Oxide Semiconductor (LDMOS) with linear graded drift region width is proposed. The device features a specific drift region with the lateral width increasing from source to drain, which modulates the electric field distribution and increases the doping concentration. The breakdown voltage exceeds 600V on the proposed LDMOS with 1 m SOI layer, 3 m buried oxide and 60 m drift region length. The characteristics are investigated by a three dimensional simulator. The simulation results show that a 135% increase in breakdown voltage and 5 times increase in figure of merits are achieved for the proposed device when compared with those of the conventional device.

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Variation of Lateral Width Technique in SoI High-Voltage Lateral Double-Diffused Metal–Oxide–Semiconductor Transistors Using High-k Dielectric

Cited by 68 publications

References 14 publications

Effective Concentration Profile: A Novel 1-D Analysis of the Variation of Lateral Thickness (VLT) Lateral Power Devices

Effective Concentration Profile: A Novel 1-D Analysis of the Variation of Lateral Thickness (VLT) Lateral Power Devices

Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer

Novel high-voltage LDMOS with linear graded drift region width

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