Variation-Aware Fault Grading

Czutro, Alexander; Imhof, Michael E.; Jiang, Jie; Mumtaz, Abdullah; Sauer, Matthias; Becker, Bernd; Polian, Ilia; Wunderlich, Hans-Joachim

doi:10.1109/ats.2012.14

Cited by 11 publications

(5 citation statements)

References 26 publications

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“…After the first few calibration loops, overflows become relatively rare and the simulation system is able to stay in the high performance full-speed simulation loop for most of the passes. This is even true in variation analysis where gate timing is slightly altered between simulations [Czutro et al 2012;Sauer et al 2014], because the efficient collision detection and glitch filtering still limits the number of hazards on a signal. The waveform capacities are stored to disk and reloaded in subsequent simulations of the same design (Step three in Figure 6) to initialize the capacities and avoid most calibrations altogether.…”

Section: The Main Simulation Loopsmentioning

confidence: 94%

“…The simulator combines for the first time the versatility of event-based timing simulation and multidimensional parallelism for maximum speedup. Specialized versions of this simulator have already been used successfully for variation analysis [Czutro et al 2012;Sauer et al 2014] and power simulation [Holst et al 2012]. Multidimensional parallelism has been used very successfully to speed up logic simulation.…”

Section: Introductionmentioning

confidence: 99%

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High-Throughput Logic Timing Simulation on GPGPUs

Holst

Imhof

Wunderlich

2015

ACM Trans. Des. Autom. Electron. Syst.

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Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands.The new simulation system presented here is able to accelerate such tasks by more than two orders of magnitude and provides for the first time fast and comprehensive timing simulations for industrialsized designs. Hazards, pulse-filtering, and pin-to-pin delay are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more realistic delay models and further applications.A sophisticated mapping with efficient memory utilization and access patterns as well as minimal synchronizations and control flow divergence is able to use the full potential of GPGPU architectures. To provide such a mapping, we combine for the first time the versatility of event-based timing simulation and multidimensional parallelism used in GPU-based gate-level simulators. The result is a throughput-optimized timing simulation algorithm, which runs many simulation instances in parallel and at the same time fully exploits gate-parallelism within the circuit.

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Section: The Main Simulation Loopsmentioning

confidence: 94%

Section: Introductionmentioning

confidence: 99%

High-Throughput Logic Timing Simulation on GPGPUs

Holst

Imhof

Wunderlich

2015

ACM Trans. Des. Autom. Electron. Syst.

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“…If many SDFs have a size that is close to the slack of a sensitizable path, they may be detectable in some circuit instances but undetectable in others. Fault coverage metrics employed in previous work [19] that did not incorporate accurate detectability status yielded quite low coverages (5% to 35%) for test sets that achieve 76% to 86% fault efficiency according to Eq. 1.…”

Section: B Fault Detection Under Variationsmentioning

confidence: 99%

Variation-aware deterministic ATPG

Sauer

Polian

Imhof

et al. 2014

2014 19th IEEE European Test Symposium (ETS)

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In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-In technologies affected by variability, the detection status of a small-delay fault may vary among manufactured circuit instances. The same fault may be detected, missed or provably undetectable in different circuit instances. We introduce the first complete flow to accurately evaluate and systematically maximize the test quality under variability. As the number of possible circuit instances is infinite, we employ statistical analysis to obtain a test set that achieves a fault-efficiency target with an user-defined confidence level. The algorithm combines a classical path-oriented test-generation procedure with a novel waveformaccurate engine that can formally prove that a small-delay fault is not detectable and does not count towards fault efficiency. Extensive simulation results demonstrate the performance of the generated test sets for industrial circuits affected by uncorrelated and correlated variations.

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“…To avoid simulating the entire test set after every removal or insertion of a test vector pair, [12] proposed to store the random delay values and test results for all iterations and test vector pairs. However, a Monte-Carlo simulation of the entire circuit is inefficient because only sufficiently long paths, which are also sensitized by the new test vector pair, can have a significant impact on the fault detection probability.…”

Section: Introductionmentioning

confidence: 99%

Incremental computation of delay fault detection probability for variation-aware test generation

Wagner

Wunderlich

2014

2014 19th IEEE European Test Symposium (ETS)

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Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead. To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE. Abstract-Large process variations in recent technology nodes present a major challenge for the timing analysis of digital integrated circuits. The optimization decisions of a statistical delay test generation method must therefore rely on the probability of detecting a target delay fault with the currently chosen test vector pairs. However, the huge number of probability evaluations in practical applications creates a large computational overhead.To address this issue, this paper presents the first incremental delay fault detection probability computation algorithm in the literature, which is suitable for the inner loop of automatic test pattern generation methods. Compared to Monte Carlo simulations of NXP benchmark circuits, the new method consistently shows a very large speedup and only a small approximation error.

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Variation-Aware Fault Grading

Cited by 11 publications

References 26 publications

High-Throughput Logic Timing Simulation on GPGPUs

High-Throughput Logic Timing Simulation on GPGPUs

Variation-aware deterministic ATPG

Incremental computation of delay fault detection probability for variation-aware test generation

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