High-Throughput Logic Timing Simulation on GPGPUs

Abstract

Many EDA tasks such as test set characterization or the precise estimation of power consumption, power droop and temperature development, require a very large number of time-aware gate-level logic simulations. Until now, such characterizations have been feasible only for rather small designs or with reduced precision due to the high computational demands.The new simulation system presented here is able to accelerate such tasks by more than two orders of magnitude and provides for the first time fast and comprehensive timing simulations for industrialsized designs. Hazards, pulse-filtering, and pin-to-pin delay are supported for the first time in a GPGPU accelerated simulator, and the system can easily be extended to even more realistic delay models and further applications.A sophisticated mapping with efficient memory utilization and access patterns as well as minimal synchronizations and control flow divergence is able to use the full potential of GPGPU architectures. To provide such a mapping, we combine for the first time the versatility of event-based timing simulation and multidimensional parallelism used in GPU-based gate-level simulators. The result is a throughput-optimized timing simulation algorithm, which runs many simulation instances in parallel and at the same time fully exploits gate-parallelism within the circuit.

Opportunities for RTL and gate level simulation using GPUs

“…In addition, eventdriven simulators require book-keeping tasks regarding which and when gates/processes toggle, leading to increased communication overhead on the GPU and more irregular memory access patterns. In our survey of prior art, we find that event-driven simulation tends to garner larger speedup numbers [2,3]. Event-based simulation is also the predominant method used by commercial simulation tools.…”

“…GPUs also present challenges to simulation acceleration, such as code translation to be able to run on GPU hardware. Other challenges include overcoming obstacles to substantial speedup such as minimizing communication overhead between host/device (CPU/GPU), efficient scheduling, and optimizing memory access patterns [2][3][4][5][6][7].…”

“…Indeed, much extensive prior research has been conducted on the topic of gate level and RTL simulation speedup using GPUs with impressive results [2][3][4][5][6]. By utilizing GPUs for parallelization, they achieve up to 1000X order of magnitude speedups [2].…”

“…Indeed, much extensive prior research has been conducted on the topic of gate level and RTL simulation speedup using GPUs with impressive results [2][3][4][5][6]. By utilizing GPUs for parallelization, they achieve up to 1000X order of magnitude speedups [2]. This is despite that simulation has been classified as a difficult program to parallelize [4,8] due to the sparsity of graph (the simulated netlist Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page.…”

Problem C

“…Commercial tools such as RocketSim have been reported to achieve up to a 23x speedup using GPUs on gate simulation [2] in 2013 on very large designs (hundreds of millions of gates). More recent research has exploited both gate-parallelism and stimuliparallelism, similar to this proposed problem, to achieve up to 1000X speedup for timing-aware gate-level simulation [3], although only with two-value simulation and on a restricted gate set. Many of the techniques described in these prior research publications may be useful references for this problem.…”