Variable voltage scheduling

Abstract

This paper presents a low power design technique at the behavioral synthesis stage. Scheduling technique for low power is studied and a theoretical foundation is established. The equation for dynamic power, P dyn = V 2 dd C load f switch , i s u s e d a s a b asis. The voltage applied to the functional units is varied, slowing down the functional unit throughput, reducing the power but meeting the throughput constraint for the entire system. The input to our problem is an unscheduled data ow graph with a timing constraint. The goal is to establish a voltage value at which each of the operations of the data ow graph would be p erformed and thereby xing the latency for the operation such that the total timing constraint for the system is met. We give an exact algorithm to minimize the system's power. The timing constraint for our system could be any value more than or equal to the critical path. The experimental results for some High-Level Synthesis benchmarks show considerable reduction in the power consumption. For tighter timing constraints, the maximum reduction is about 40% by using supply voltages 5V and 3V and a maximum reduction of about 46% using supply voltages 5V, 3V and 2.4V. For larger timing constraints, the maximum reduction is about 64% by using supply voltages 5V and 3V and a maximum reduction of about 74% using supply voltages 5V, 3V and 2.4V.

Decoupling Capacitors for Multi-Voltage Power Distribution Systems

“…The voltage transfer function of a power distribution system with two power supply voltages and decoupling capacitors, represented by an RLC network, is (7) where Rearranging, (7) can be written as (8) where Equations (7) and (8) are valid only for nonzero frequency, i.e., for . Note from (7), that if all of the parameters of a power distribution system are identical, the transfer function equals 0.5 and is independent of frequency. The dependence of the voltage transfer function on the parameters of the power distribution system is discussed below.…”

“…This scheme results in a smaller area as compared to parallel architectures. The problem of using multiple supply voltages for reducing the power requirements has been investigated in the area of high-level synthesis for low-power [6], [7]. While it is possible to provide many supply voltages, in practice such a scenario is expensive.…”

Low-power RT-level synthesis techniques: a tutorial

“…Overhead of level converters can be mitigated by doing conversions at register boundaries and embedding the level conversion inside the flip flops (see [4] for details.) A polynomial time algorithm for multiple-voltage scheduling of performance-constrained non-pipelined designs is presented by Raje and Sarrafzadeh in [5]. The idea is to establish a supply voltage level for each of the operations in a data flow graph, thereby, fixing the latency of that operation.…”

System-level power optimization: techniques and tools

“…Various behavioral synthesis techniques have been proposed to deal with multiple supply voltages [Chang and Pedram 1997;Raje and Sarrafzadeh 1995;Johnson and Roy 1996]. The key idea in these approaches is to save power in noncritical functional units by powering them with a down-scaled supply voltage.…”