Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes

Le, Khoa; Declercq, David; Ghaffari, Fakhreddine; Kessal, Lounis; Boncalo, Oana; Savin, Valentin

doi:10.1109/tcsi.2017.2777802

Cited by 14 publications

(3 citation statements)

References 31 publications

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“…For quasi-cyclic LDPC (QC-LDPC) codes, the recently described Variable Node Shift Architecture (VNSA) implements PGDBF without requiring any RNG [17]. In the VNSA, a unique pre-generated noise sample is hard-coded into each variable node.…”

Section: Methodsmentioning

confidence: 99%

“…In the same year, Noisy Gradient Descent Bit Flipping (NGDBF) was described for the Gaussian channel [9] and the related Probabilistic Gradient Descent Bit Flipping (PGDBF) algorithm for the BSC [10]. These works led to a number of algorithm and hardware improvements for NGDBF [11]- [13] and PGDBF [14]- [17], along with potential specialized applications in solid-state storage [18]. A related approach, known as the Improved Differential Binary (IDB) decoder, was also proposed in 2014 [19].…”

Section: B Noise Enhanced Decodersmentioning

confidence: 99%

See 1 more Smart Citation

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders

Winstead

Tithi

Boutillon

et al. 2018

2018 IEEE 10th International Symposium on Turbo Codes &Amp; Iterative Information Processing (ISTC)

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This paper offers a review of recent developments in non-deterministic error correction decoding methods, which can be described in two broad classes. The first class uses stochastic computation to emulate the arithmetic operations of conventional decoding algorithms. The second class achieves noise enhancement by randomly perturbing the calculations of a standard decoder. Stochastic decoders inherit analysis techniques from the conventional algorithms they emulate, but the noiseenhanced algorithms are newer, more difficult to explain, and not yet fully understood. We describe a Markov chain analysis technique to both explain and optimize noise enhancement in these algorithms. Circuit implementation is also discussed, including both conventional hardware architectures and circuits based on memristor threshold logic, where memristor non-determinism can be exploited for noise enhancement.

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Section: Methodsmentioning

confidence: 99%

Section: B Noise Enhanced Decodersmentioning

confidence: 99%

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders

Winstead

Tithi

Boutillon

et al. 2018

2018 IEEE 10th International Symposium on Turbo Codes &Amp; Iterative Information Processing (ISTC)

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“…Comparison between the proposed BF decoders and the state-of-the-art LDPC decoders. work K.Le'17[26] M.Ismail'13[20] J.Cho'10 [28] Nguyen-Ly'16[21] Since the SC module is not implemented in this NS-PPBF implementation, these average values of NS-PPBF are bounds on the achievable results and they are not really practical relevance.…”

mentioning

confidence: 99%

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

Ghaffari

Kessal

et al. 2019

IEEE Trans. Circuits Syst. I

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This paper presents a new Bit Flipping (BF) decoder, called the Probabilistic Parallel Bit Flipping (PPBF) for Low-Density Parity-Check (LDPC) codes on the Binary Symmetric Channel. In the PPBF, the flipping operation is performed in a probabilistic manner which is shown to improve significantly the error correction performance. The advantage of the PPBF also comes from the fact that no global computation is required during the decoding process and that all the computations can be executed in the local computing units and in-parallel. The PPBF provides a considerable improvement of the operating frequency and complexity, compared to other known BF decoders, while obtaining a significant gain in error correction. An improved version of the PPBF, called non-syndrome PPBF (NS-PPBF) is also introduced, in which the global syndrome check is moved out of the critical path and a new terminating mechanism is proposed. In order to show the superiority of the new decoders in terms of hardware efficiency and decoding throughput, the corresponding hardware architectures are presented in the second part of the paper. The ASIC synthesis results confirm that the operating frequency of the proposed decoders is significantly improved, compared to that of the BF decoders in the literature while requiring lower complexity to be efficiently implemented.

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A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes

Cui

Lin

Song

et al. 2019

2019 IEEE International Symposium on Circuits and Systems (ISCAS)

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Variable-Node-Shift Based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes

Abstract: International audienc

Cited by 14 publications

References 31 publications

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders

Recent Advances on Stochastic and Noise Enhanced Methods in Error Correction Decoders

A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes

A New Probabilistic Gradient Descent Bit Flipping Decoder for LDPC Codes

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