Variable area MWIR diodes on HgCdTe/Si grown by molecular beam epitaxy

Analysis of leakage currents in MOCVD grown GaInAsSb based photodetectors operating at 2 µm

“…Then, the samples were etched in concentrated hydrochloric acid (HCl) to remove the native oxide layer. Mesas were defined using the standard photolithographic technique, and the samples were etched using a solution of (Received September 6, 2005; accepted April 16,2006) HCl: H 2 O 2 : NaK tartrate (66 mL: 18 mL: 24 g in 1 L of solution) beyond the junction to electrically isolate the devices. Different sized circular mesa diodes were fabricated (diameter 5 75 mm, 100 mm, 150 mm, 200 mm, 300 mm, 500 mm, and 1,000 mm).…”

Modeling of the zero-bias resistance-area product of long wavelength infrared HgCdTe-on-Si diodes fabricated from molecular beam epitaxy-grown epitaxial layers

“…The diode configuration under discussion corresponds to a one-sided P-on-n junction, whose diffusion current impedance is described by the following equation: 10 (2) where k is the Boltzmann constant, q is the fundamental charge of an electron, and T is the temperature of the sample. S r is the surface recombination velocity at the epi-substrate interface, n i is the intrinsic carrier concentration, t is the thickness, and n 0 is the concentration of the electrons in the base n-epilayer.…”

“…(211) Si substrates. [2][3][4][5][6] These arrays are generally operated at 77 K, where contribution of dislocations is within tolerable limits for some tactical applications. High dislocation density in the range of mid-10 6 cm Ϫ2 in these epitaxial layers has, however, prevented the realization of uniform LWIR arrays suitable for operation at 40 K for some strategic applications.…”

Realization of very long wavelength infrared photovoltaic detector arrays on mercury cadmium telluride epitaxial layers grown on Si substrates

“…Short wavelength infrared and mid-wavelength infrared detector arrays with state-of-the-art performance levels at 77 K have already been reported in the literature using HgCdTe-on-Si material. [1][2][3][4][5][6][7] However, high dislocation densities in the mid-10 6 cm À2 range in HgCdTe/Si material are proving to be a bottleneck in realizing high-performance uniform arrays operating at 40 K. Current efforts toward reducing dislocation density include (1) using various buffer layers, such as CdTe, CdSeTe, and CdZnTe to terminate the buffer layer growth with lattice-matching conditions for epitaxial HgCdTe growth [8][9][10][11] and (2) bending of dislocations away from the active diode area using dislocation gettering techniques. [12][13][14][15] In addition, control of core charges of dislocations toward higher core charge values in order to enhance the shunt resistance of an individual dislocation has been recently suggested as an alternative method to reduce the contribution of dislocations.…”