Variability-tolerant NoC link design

Process variability-induced NoC link failure: A probabilistic model

“…Their model provided the failure rates of micro architectural blocks as a function of frequency and the amount of variations. While Sarangi et al considered only systematic and random variations resulting from front-end fabrication processes to get the normalized gate delay, we consider systematic and random variations resulting from both the front-end and the back-end fabrication processes to get the total interconnect delay variations [15].…”

“…They showed that process variations in NoC links cause links to have different delays. Our work in [15] uses link delay variations to calculate the optimum number of repeaters that tolerates process variations effects.…”

“…Additionally, calibration and driver/receiver circuit reconfiguration techniques were proposed to encompass different sources of variations [14]. Our work in [17] proposed statistical current margin that tolerates process variations.…”

“…Using this spherical correlation model with the geoR statistical package [34] of R [35], we generate within-die systematic variation maps for gate length, threshold voltage, line width, and line height for different technologies [15]. Fig.…”

“…Thus, we propose a variability-tolerant NoC link design methodologies for both voltage mode (VM) and CM interconnects [15][16][17]. In these methodologies, we model variability to calculate a statistical guard/ margin for current or delay that tolerates random and systematic variability with a defined power cost.…”