Variability-aware NoC geometry and topology scaling

Process variability-induced NoC link failure: A probabilistic model

“…Systematic variations in device and interconnect geometries will cause systematic deviation components of delay and current, as shown in Fig. 1 and detailed in our previous work [15][16][17].…”

“…The NoC link geometry variations are used to calculate the interconnect delay/current variations in a statistical approach. In our previous work [15][16][17], we proposed a statistical NoC link design methodology for both CM and VM NoC links. We extended our previous work to calculate NoC link failure probability due to delay variations of VM or current variations of CM interconnect.…”

“…Their simulation results show how the delay scales with link length and driver size [26]. Our work in [16] shows how delay variations scale with interconnect geometry, like link length, width, height, and spacing.…”

“…Thus, we propose a variability-tolerant NoC link design methodologies for both voltage mode (VM) and CM interconnects [15][16][17]. In these methodologies, we model variability to calculate a statistical guard/ margin for current or delay that tolerates random and systematic variability with a defined power cost.…”