Value assignment of Adjustable Delay Buffers for clock skew minimization in multi-voltage mode designs

Joo

Proceedings of the 50th Annual Design Automation Conference

2013

Meeting clock skew constraint is one of the most important tasks in the synthesis of clock trees. Moreover, the problem becomes much hard to tackle as the delay of clock signals varies dynamically during execution. Recently, it is shown that adjustable delay buffer (ADB) whose delay can be adjusted dynamically can solve the clock skew variation problem effectively. However, inserting ADBs requires non-negligible area and control overhead. Thus, all previous works have invariably aimed at minimizing the number of ADBs to be inserted, particularly under the environment of multiple power modes in which the operating voltage applied to some modules varies as the power mode changes. In this work, unlike the previous works which have solved the ADB minimization problem heuristically or locally optimally, we propose an elegant and easily adoptable solution to overcome the limitation of the previous works. Precisely, we propose an O(n log n) time (bottom-up traversal) algorithm that (1) optimally solves the problem of minimizing the number of ADBs to be inserted with continuous delay of ADBs and (2) enables solving the ADB insertion problem with discrete delay of ADBs to be greatly simple and predictable. In addition, we propose (3) a systematic solution to an important extension to the problem of buffer sizing combined with the ADB insertion to further reduce the ADBs to be used.

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem

Joo

Proceedings of the 50th Annual Design Automation Conference

2013

2015 International Symposium on Next-Generation Electronics (ISNE)

“…Because the variation of clock skews in different power modes can be very large, insertion of adjustable delay buffers (ADBs) in the post-silicon process is a widely used methodology to reduce the clock skews in the multiple power modes designs [1][2][3][4][5]. The delay of an ADB is controlled by its control circuit and delay control pins, clock skew variation caused by process variation in different power modes can be tuned by properly replacing some normal clock buffers with ADBs, and assign suitable delay values by properly setting the delay control pins, so that the clock skew constraint in each power mode can be satisfied.…”

Section: Introductionmentioning

confidence: 99%

A window-based methodology for ADBs insertion and clock gating design in multiple power modes

Cheng

2015

In the low power design of integrated circuits, multiple power modes and clock gating are the two common techniques to reduce dynamic power consumption. In the multiple power modes designs, replacing some of the normal buffers with adjustable delay buffers (ADBs) and assign different delay values in different power modes is one of the promising solutions to satisfy the clock skew constraint, and clock gate splitting is necessary to satisfy the enable timing constraint in clock gating designs. However, both ADBs insertion and gate splitting increase the hardware cost. In this paper, under both the enable timing constraint and clock skew constraint, we propose a skew-window based methodology to reduce the total hardware cost of ADBs and clock gates simultaneously. In comparison with when only ADBs insertion or clock gate splitting technique is applied, experimental results show that our methodology can satisfy the constraints in all the power modes and reduce the hardware cost effectively.

2014 International Symposium on Next-Generation Electronics (ISNE)

“…During the post-silicon stage, some research works [1,2] use ADBs (adjustable delay buffers) to adjust the delay of the clock path for eliminating the clock skew of a multi-voltage design. Moreover, in recent years, the effect of PVT variations are considered in [3][4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

PVT-variations-tolerant clock design using self-correcting adjustable delay buffers

Huang

2014

As the process technology scaling, the tolerance to PVT (process/ voltage/temperature) variation has become a serious concern. During the post-silicon stage, ADBs (adjustable delay buffers) can be used to adjust the delay of the clock path for eliminating the clock skew. However, in fact, unless that the clock tree has a self-correcting mechanism, the clock skew caused by PVT variations still cannot be properly controlled. In this paper, we propose the first self-correcting ADB system to control the clock skew during circuit execution. Experimental results show that our design methodology can achieve very good results.